[PATCHv2 2/2] target/arm: enable Small Translation tables in max CPU

[PATCHv2 2/2] target/arm: enable Small Translation tables in max CPU

[remi.denis.courmont]

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
---
 target/arm/cpu64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 7cf9fc4bc6..da24f94baa 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -669,6 +669,7 @@ static void aarch64_max_initfn(Object *obj)
         t = cpu->isar.id_aa64mmfr2;
         t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
         t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
+        t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
         cpu->isar.id_aa64mmfr2 = t;
 
         /* Replicate the same data to the 32-bit id registers.  */
-- 
2.30.0

Re: [PATCHv2 2/2] target/arm: enable Small Translation tables in max CPU

[Richard Henderson]

On 1/7/21 11:08 PM, remi.denis.courmont@huawei.com wrote:
> From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> 
> Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> ---
>  target/arm/cpu64.c | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCHv2 2/2] target/arm: enable Small Translation tables in max CPU

[Peter Maydell]

On Fri, 8 Jan 2021 at 09:08, <remi.denis.courmont@huawei.com> wrote:
>
> From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
>
> Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> ---
>  target/arm/cpu64.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 7cf9fc4bc6..da24f94baa 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -669,6 +669,7 @@ static void aarch64_max_initfn(Object *obj)
>          t = cpu->isar.id_aa64mmfr2;
>          t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
>          t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
> +        t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
>          cpu->isar.id_aa64mmfr2 = t;

I've applied this series to target-arm.next; thanks.

It looks like you forgot to send the series as a threaded set of
emails with a cover letter email. This confuses our tools which
find patches in the mailing list (so your series doesn't show up
on patchew or in the 'patches' tool's list of patches), and it
also means I'm likely to miss it when I go through my emails
manually. I dealt with this one manually, but it's a lot more
work for me to do so and it was only really feasible because
there were only two patches in the series.

For future submissions, please can you make sure you send
multi-patch series with a 00/nn cover letter email and with
all the patches in the series being followups to that cover
letter. git send-email will get all the threading details
right for you.
(Single standalone patches don't need a cover letter.)
https://wiki.qemu.org/Contribute/SubmitAPatch has more
info on our patch submission recommendations.

thanks
-- PMM