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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id b10sm12840748pgh.15.2021.01.09.04.36.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 04:36:18 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v3 3/6] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Date: Sat, 9 Jan 2021 20:35:42 +0800 Message-Id: <20210109123545.12001-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210109123545.12001-1-bmeng.cn@gmail.com> References: <20210109123545.12001-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=bmeng.cn@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Usually the approach is that the device on the other end of the line is going to reset its state anyway, so there's no need to actively signal an irq line change during the reset hook. Move imx_spi_update_irq() out of imx_spi_reset(), along with the disabling of chip selects, to a new function imx_spi_soft_reset() that is called when the controller is disabled. Signed-off-by: Bin Meng --- Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() hw/ssi/imx_spi.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 8d429e703f..880939f595 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -241,9 +241,20 @@ static void imx_spi_reset(DeviceState *dev) imx_spi_rxfifo_reset(s); imx_spi_txfifo_reset(s); + s->burst_length = 0; +} + +static void imx_spi_soft_reset(IMXSPIState *s) +{ + int i; + + imx_spi_reset(DEVICE(s)); + imx_spi_update_irq(s); - s->burst_length = 0; + for (i = 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) @@ -351,12 +362,8 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value, s->regs[ECSPI_CONREG] = value; if (!imx_spi_is_enabled(s)) { - /* device is disabled, so this is a reset */ - imx_spi_reset(DEVICE(s)); - - for (int i = 0; i < ECSPI_NUM_CS; i++) { - qemu_set_irq(s->cs_lines[i], 1); - } + /* device is disabled, so this is a soft reset */ + imx_spi_soft_reset(s); return; } -- 2.25.1