From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v3 12/30] target/arm: Fix SCTLR_B test for TCGv_i64 load/store
Date: Mon, 11 Jan 2021 09:00:55 -1000 [thread overview]
Message-ID: <20210111190113.303726-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org>
Just because operating on a TCGv_i64 temporary does not
mean that we're performing a 64-bit operation. Restrict
the frobbing to actual 64-bit operations.
This bug is not currently visible because all current
users of these two functions always pass MO_64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index efcb393b99..bf1c0f7279 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -982,7 +982,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
tcg_gen_qemu_ld_i64(val, addr, index, opc);
/* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b) {
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
tcg_gen_rotri_i64(val, val, 32);
}
@@ -1001,7 +1001,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
TCGv addr = gen_aa32_addr(s, a32, opc);
/* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b) {
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_rotri_i64(tmp, val, 32);
tcg_gen_qemu_st_i64(tmp, addr, index, opc);
--
2.25.1
next prev parent reply other threads:[~2021-01-11 19:18 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-11 19:00 [PATCH v3 00/30] target/arm: enforce alignment Richard Henderson
2021-01-11 19:00 ` [PATCH v3 01/30] target/arm: Fix decode of align in VLDST_single Richard Henderson
2021-01-11 19:00 ` [PATCH v3 02/30] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
2021-01-11 19:00 ` [PATCH v3 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
2021-01-11 19:00 ` [PATCH v3 04/30] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
2021-01-11 19:00 ` [PATCH v3 05/30] target/arm: Introduce CPUARMTBFlags Richard Henderson
2021-01-11 19:00 ` [PATCH v3 06/30] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
2021-01-11 19:00 ` [PATCH v3 07/30] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
2021-01-11 19:00 ` [PATCH v3 08/30] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
2021-01-11 19:00 ` [PATCH v3 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
2021-01-11 19:00 ` [PATCH v3 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
2021-01-11 19:00 ` [PATCH v3 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
2021-01-11 19:00 ` Richard Henderson [this message]
2021-01-11 19:00 ` [PATCH v3 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Richard Henderson
2021-01-11 19:00 ` [PATCH v3 14/30] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2021-01-11 19:00 ` [PATCH v3 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2021-01-11 19:00 ` [PATCH v3 16/30] target/arm: Enforce alignment for LDM/STM Richard Henderson
2021-01-11 19:01 ` [PATCH v3 17/30] target/arm: Enforce alignment for RFE Richard Henderson
2021-01-11 19:01 ` [PATCH v3 18/30] target/arm: Enforce alignment for SRS Richard Henderson
2021-01-11 19:01 ` [PATCH v3 19/30] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2021-01-11 19:01 ` [PATCH v3 20/30] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2021-01-11 19:01 ` [PATCH v3 21/30] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 23/30] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 24/30] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
2021-01-11 19:01 ` [PATCH v3 25/30] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
2021-01-11 19:01 ` [PATCH v3 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
2021-01-11 19:01 ` [PATCH v3 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
2021-01-11 19:01 ` [PATCH v3 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 30/30] target/arm: Enforce alignment for sve LD1R Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210111190113.303726-13-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).