From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v3 20/30] target/arm: Enforce alignment for VLDR/VSTR
Date: Mon, 11 Jan 2021 09:01:03 -1000 [thread overview]
Message-ID: <20210111190113.303726-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.c.inc | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index f50afb23e7..e20d9c7ba6 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -1364,11 +1364,11 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a)
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i32();
if (a->l) {
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN);
vfp_store_reg32(tmp, a->vd);
} else {
vfp_load_reg32(tmp, a->vd);
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN);
}
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(addr);
@@ -1398,11 +1398,11 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i32();
if (a->l) {
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
vfp_store_reg32(tmp, a->vd);
} else {
vfp_load_reg32(tmp, a->vd);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
}
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(addr);
@@ -1439,11 +1439,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i64();
if (a->l) {
- gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4);
vfp_store_reg64(tmp, a->vd);
} else {
vfp_load_reg64(tmp, a->vd);
- gen_aa32_st64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4);
}
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(addr);
--
2.25.1
next prev parent reply other threads:[~2021-01-11 19:22 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-11 19:00 [PATCH v3 00/30] target/arm: enforce alignment Richard Henderson
2021-01-11 19:00 ` [PATCH v3 01/30] target/arm: Fix decode of align in VLDST_single Richard Henderson
2021-01-11 19:00 ` [PATCH v3 02/30] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
2021-01-11 19:00 ` [PATCH v3 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
2021-01-11 19:00 ` [PATCH v3 04/30] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
2021-01-11 19:00 ` [PATCH v3 05/30] target/arm: Introduce CPUARMTBFlags Richard Henderson
2021-01-11 19:00 ` [PATCH v3 06/30] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
2021-01-11 19:00 ` [PATCH v3 07/30] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
2021-01-11 19:00 ` [PATCH v3 08/30] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
2021-01-11 19:00 ` [PATCH v3 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
2021-01-11 19:00 ` [PATCH v3 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
2021-01-11 19:00 ` [PATCH v3 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
2021-01-11 19:00 ` [PATCH v3 12/30] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
2021-01-11 19:00 ` [PATCH v3 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Richard Henderson
2021-01-11 19:00 ` [PATCH v3 14/30] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2021-01-11 19:00 ` [PATCH v3 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2021-01-11 19:00 ` [PATCH v3 16/30] target/arm: Enforce alignment for LDM/STM Richard Henderson
2021-01-11 19:01 ` [PATCH v3 17/30] target/arm: Enforce alignment for RFE Richard Henderson
2021-01-11 19:01 ` [PATCH v3 18/30] target/arm: Enforce alignment for SRS Richard Henderson
2021-01-11 19:01 ` [PATCH v3 19/30] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2021-01-11 19:01 ` Richard Henderson [this message]
2021-01-11 19:01 ` [PATCH v3 21/30] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 23/30] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 24/30] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
2021-01-11 19:01 ` [PATCH v3 25/30] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
2021-01-11 19:01 ` [PATCH v3 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
2021-01-11 19:01 ` [PATCH v3 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
2021-01-11 19:01 ` [PATCH v3 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 30/30] target/arm: Enforce alignment for sve LD1R Richard Henderson
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