From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v3 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single)
Date: Mon, 11 Jan 2021 09:01:12 -1000 [thread overview]
Message-ID: <20210111190113.303726-30-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210111190113.303726-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7765c15e0c..ec8e488b11 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3786,6 +3786,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
int index = is_q << 3 | S << 2 | size;
int xs, total;
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
+ MemOp mop;
if (extract32(insn, 31, 1)) {
unallocated_encoding(s);
@@ -3847,6 +3848,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31,
scale, total);
+ mop = finalize_memop(s, scale);
tcg_ebytes = tcg_const_i64(1 << scale);
for (xs = 0; xs < selem; xs++) {
@@ -3854,8 +3856,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
/* Load and replicate to all elements */
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr,
- get_mem_index(s), s->be_data + scale);
+ tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop);
tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt),
(is_q + 1) * 8, vec_full_reg_size(s),
tcg_tmp);
@@ -3863,9 +3864,9 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
} else {
/* Load/store one element per register */
if (is_load) {
- do_vec_ld(s, rt, index, clean_addr, scale | s->be_data);
+ do_vec_ld(s, rt, index, clean_addr, mop);
} else {
- do_vec_st(s, rt, index, clean_addr, scale | s->be_data);
+ do_vec_st(s, rt, index, clean_addr, mop);
}
}
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
--
2.25.1
next prev parent reply other threads:[~2021-01-11 19:41 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-11 19:00 [PATCH v3 00/30] target/arm: enforce alignment Richard Henderson
2021-01-11 19:00 ` [PATCH v3 01/30] target/arm: Fix decode of align in VLDST_single Richard Henderson
2021-01-11 19:00 ` [PATCH v3 02/30] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
2021-01-11 19:00 ` [PATCH v3 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
2021-01-11 19:00 ` [PATCH v3 04/30] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
2021-01-11 19:00 ` [PATCH v3 05/30] target/arm: Introduce CPUARMTBFlags Richard Henderson
2021-01-11 19:00 ` [PATCH v3 06/30] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
2021-01-11 19:00 ` [PATCH v3 07/30] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
2021-01-11 19:00 ` [PATCH v3 08/30] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
2021-01-11 19:00 ` [PATCH v3 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
2021-01-11 19:00 ` [PATCH v3 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
2021-01-11 19:00 ` [PATCH v3 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
2021-01-11 19:00 ` [PATCH v3 12/30] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
2021-01-11 19:00 ` [PATCH v3 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Richard Henderson
2021-01-11 19:00 ` [PATCH v3 14/30] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2021-01-11 19:00 ` [PATCH v3 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2021-01-11 19:00 ` [PATCH v3 16/30] target/arm: Enforce alignment for LDM/STM Richard Henderson
2021-01-11 19:01 ` [PATCH v3 17/30] target/arm: Enforce alignment for RFE Richard Henderson
2021-01-11 19:01 ` [PATCH v3 18/30] target/arm: Enforce alignment for SRS Richard Henderson
2021-01-11 19:01 ` [PATCH v3 19/30] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2021-01-11 19:01 ` [PATCH v3 20/30] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2021-01-11 19:01 ` [PATCH v3 21/30] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 23/30] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2021-01-11 19:01 ` [PATCH v3 24/30] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
2021-01-11 19:01 ` [PATCH v3 25/30] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
2021-01-11 19:01 ` [PATCH v3 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
2021-01-11 19:01 ` [PATCH v3 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
2021-01-11 19:01 ` [PATCH v3 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
2021-01-11 19:01 ` Richard Henderson [this message]
2021-01-11 19:01 ` [PATCH v3 30/30] target/arm: Enforce alignment for sve LD1R Richard Henderson
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