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[173.197.107.21]) by smtp.gmail.com with ESMTPSA id i7sm3771687pfc.50.2021.01.13.18.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jan 2021 18:17:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/24] tcg/tci: Add special tci_movi_{i32,i64} opcodes Date: Wed, 13 Jan 2021 16:16:47 -1000 Message-Id: <20210114021654.647242-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210114021654.647242-1-richard.henderson@linaro.org> References: <20210114021654.647242-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The normal movi opcodes are going away. We need something for TCI to use internally. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 8 ++++++++ tcg/tci.c | 4 ++-- tcg/tci/tcg-target.c.inc | 4 ++-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 70a76646c4..43711634f6 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -278,6 +278,14 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) #include "tcg-target.opc.h" #endif +#ifdef TCG_TARGET_INTERPRETER +/* These opcodes are only for use between the tci generator and interpreter. */ +DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) +#if TCG_TARGET_REG_BITS == 64 +DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) +#endif +#endif + #undef TLADDR_ARGS #undef DATA64_ARGS #undef IMPL diff --git a/tcg/tci.c b/tcg/tci.c index 2bcc4409be..2311aa7d3a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -593,7 +593,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t1 = tci_read_r32(regs, &tb_ptr); tci_write_reg32(regs, t0, t1); break; - case INDEX_op_movi_i32: + case INDEX_op_tci_movi_i32: t0 = *tb_ptr++; t1 = tci_read_i32(&tb_ptr); tci_write_reg32(regs, t0, t1); @@ -864,7 +864,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t1 = tci_read_r64(regs, &tb_ptr); tci_write_reg64(regs, t0, t1); break; - case INDEX_op_movi_i64: + case INDEX_op_tci_movi_i64: t0 = *tb_ptr++; t1 = tci_read_i64(&tb_ptr); tci_write_reg64(regs, t0, t1); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d5a4d9d37c..e9e5f94c04 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -529,13 +529,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, uint8_t *old_code_ptr = s->code_ptr; uint32_t arg32 = arg; if (type == TCG_TYPE_I32 || arg == arg32) { - tcg_out_op_t(s, INDEX_op_movi_i32); + tcg_out_op_t(s, INDEX_op_tci_movi_i32); tcg_out_r(s, t0); tcg_out32(s, arg32); } else { tcg_debug_assert(type == TCG_TYPE_I64); #if TCG_TARGET_REG_BITS == 64 - tcg_out_op_t(s, INDEX_op_movi_i64); + tcg_out_op_t(s, INDEX_op_tci_movi_i64); tcg_out_r(s, t0); tcg_out64(s, arg); #else -- 2.25.1