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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id g194sm9247219wme.39.2021.01.14.08.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 08:21:49 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Subject: [PULL v2 68/69] target/mips: Remove vendor specific CPU definitions Date: Thu, 14 Jan 2021 17:20:16 +0100 Message-Id: <20210114162016.2901557-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210114162016.2901557-1-f4bug@amsat.org> References: <20210114162016.2901557-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Richard Henderson , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Vendor specific CPU definitions are not very useful. Use the ISA definitions instead, which are more helpful when looking at the various CPU definitions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210112210152.2072996-4-f4bug@amsat.org> --- target/mips/mips-defs.h | 5 ----- target/mips/cpu-defs.c.inc | 12 +++++++----- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 3704db85532..0a12d982a72 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -60,9 +60,6 @@ #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) -#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) -#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) -#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) #define CPU_MIPS64 (ISA_MIPS3) @@ -86,8 +83,6 @@ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) -#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT) - /* * Strictly follow the architecture standard: * - Disallow "special" instruction handling for PMON/SPIM. diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 9f7bac87932..e03b2a998cd 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -531,7 +531,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 40, .PABITS = 32, - .insn_flags = CPU_VR54XX, + .insn_flags = CPU_MIPS4 | INSN_VR54XX, .mmu_type = MMU_TYPE_R4000, }, { @@ -781,7 +781,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 40, .PABITS = 40, - .insn_flags = CPU_LOONGSON2E, + .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E, .mmu_type = MMU_TYPE_R4000, }, { @@ -801,7 +801,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 40, .PABITS = 40, - .insn_flags = CPU_LOONGSON2F, + .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI, .mmu_type = MMU_TYPE_R4000, }, { @@ -830,7 +830,8 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 42, .PABITS = 48, - .insn_flags = CPU_LOONGSON3A, + .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | + ASE_LMMI | ASE_LEXT, .mmu_type = MMU_TYPE_R4000, }, { @@ -887,7 +888,8 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 48, .PABITS = 48, - .insn_flags = CPU_LOONGSON3A, + .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | + ASE_LMMI | ASE_LEXT, .mmu_type = MMU_TYPE_R4000, }, { -- 2.26.2