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[217.232.52.240]) by smtp.gmail.com with ESMTPSA id i8sm6577604eds.72.2021.01.16.00.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Jan 2021 00:40:38 -0800 (PST) Date: Sat, 16 Jan 2021 09:40:35 +0100 From: Thomas Huth To: Peter Maydell Subject: Re: [PATCH 06/11] hw/m68k/next-cube: Move int_status and int_mask to NeXTPC struct Message-ID: <20210116094035.2af2b927@tuxfamily.org> In-Reply-To: <20210115201206.17347-7-peter.maydell@linaro.org> References: <20210115201206.17347-1-peter.maydell@linaro.org> <20210115201206.17347-7-peter.maydell@linaro.org> X-Mailer: Claws Mail 3.17.8 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=209.85.208.46; envelope-from=th.huth@gmail.com; helo=mail-ed1-f46.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Am Fri, 15 Jan 2021 20:12:01 +0000 schrieb Peter Maydell : > All the code which accesses int_status and int_mask is now doing > so via the NeXTPC->NeXTState indirection, so we can move these > fields into the NeXTPC struct where they belong. > > Signed-off-by: Peter Maydell > --- > hw/m68k/next-cube.c | 33 ++++++++++++++++----------------- > 1 file changed, 16 insertions(+), 17 deletions(-) > > diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c > index a9e57304e04..6b4bcfd4b9b 100644 > --- a/hw/m68k/next-cube.c > +++ b/hw/m68k/next-cube.c > @@ -73,9 +73,6 @@ typedef struct NextRtc { > struct NeXTState { > MachineState parent; > > - uint32_t int_mask; > - uint32_t int_status; > - > next_dma dma[10]; > qemu_irq *scsi_irq; > qemu_irq scsi_dma; > @@ -103,6 +100,8 @@ struct NeXTPC { > uint32_t scr2; > uint8_t scsi_csr_1; > uint8_t scsi_csr_2; > + uint32_t int_mask; > + uint32_t int_status; > }; > > /* Thanks to NeXT forums for this */ > @@ -243,7 +242,7 @@ static void nextscr2_write(NeXTPC *s, uint32_t > val, int size) /* clear FTU */ > if (rtc->value & 0x04) { > rtc->status = rtc->status & (~0x18); > - s->ns->int_status = s->ns->int_status & > (~0x04); > + s->int_status = s->int_status & (~0x04); > } > } > } > @@ -302,12 +301,12 @@ static uint32_t mmio_readl(NeXTPC *s, hwaddr > addr) { > switch (addr) { > case 0x7000: > - /* DPRINTF("Read INT status: %x\n", s->ns->int_status); */ > - return s->ns->int_status; > + /* DPRINTF("Read INT status: %x\n", s->int_status); */ > + return s->int_status; > > case 0x7800: > - DPRINTF("MMIO Read INT mask: %x\n", s->ns->int_mask); > - return s->ns->int_mask; > + DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); > + return s->int_mask; > > case 0xc000: > return s->scr1; > @@ -342,12 +341,12 @@ static void mmio_writel(NeXTPC *s, hwaddr addr, > uint32_t val) { > switch (addr) { > case 0x7000: > - DPRINTF("INT Status old: %x new: %x\n", s->ns->int_status, > val); > - s->ns->int_status = val; > + DPRINTF("INT Status old: %x new: %x\n", s->int_status, val); > + s->int_status = val; > break; > case 0x7800: > - DPRINTF("INT Mask old: %x new: %x\n", s->ns->int_mask, val); > - s->ns->int_mask = val; > + DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val); > + s->int_mask = val; > break; > case 0xc000: > DPRINTF("SCR1 Write: %x\n", val); > @@ -504,9 +503,9 @@ static void scr_writeb(NeXTPC *s, hwaddr addr, > uint32_t value) DPRINTF("SCSICSR CPUDMA\n"); > /* qemu_irq_raise(s->scsi_dma); */ > > - s->ns->int_status |= 0x4000000; > + s->int_status |= 0x4000000; > } else { > - s->ns->int_status &= ~(0x4000000); > + s->int_status &= ~(0x4000000); > } > if (value & SCSICSR_INTMASK) { > DPRINTF("SCSICSR INTMASK\n"); > @@ -798,14 +797,14 @@ static void next_irq(void *opaque, int number, > int level) > * this HAS to be wrong, the interrupt handlers in mach and > together > * int_status and int_mask and return if there is a hit > */ > - if (s->ns->int_mask & (1 << shift)) { > + if (s->int_mask & (1 << shift)) { > DPRINTF("%x interrupt masked @ %x\n", 1 << shift, > cpu->env.pc); /* return; */ > } > > /* second switch triggers the correct interrupt */ > if (level) { > - s->ns->int_status |= 1 << shift; > + s->int_status |= 1 << shift; > > switch (number) { > /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, > clock */ @@ -834,7 +833,7 @@ static void next_irq(void *opaque, int > number, int level) break; > } > } else { > - s->ns->int_status &= ~(1 << shift); > + s->int_status &= ~(1 << shift); > cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); > } > } Reviewed-by: Thomas Huth