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Mon, 18 Jan 2021 04:41:03 -0800 (PST) Received: from localhost ([211.108.35.36]) by smtp.gmail.com with ESMTPSA id gz2sm16514400pjb.2.2021.01.18.04.41.02 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jan 2021 04:41:03 -0800 (PST) Date: Mon, 18 Jan 2021 21:41:00 +0900 From: Minwoo Im To: Klaus Jensen Subject: Re: [PATCH v2 02/12] hw/block/nvme: fix 64 bit register hi/lo split writes Message-ID: <20210118124100.GB18718@localhost.localdomain> References: <20210118094705.56772-1-its@irrelevant.dk> <20210118094705.56772-3-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210118094705.56772-3-its@irrelevant.dk> User-Agent: Mutt/1.11.4 (2019-03-13) Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=minwoo.im.dev@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Stefan Hajnoczi , Keith Busch Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 21-01-18 10:46:55, Klaus Jensen wrote: > From: Klaus Jensen > > 64 bit registers like ASQ and ACQ should be writable by both a hi/lo 32 > bit write combination as well as a plain 64 bit write. The spec does not > define ordering on the hi/lo split, but the code currently assumes that > the low order bits are written first. Additionally, the code does not > consider that another address might already have been written into the > register, causing the OR'ing to result in a bad address. > > Fix this by explicitly overwriting only the low or high order bits for > 32 bit writes. > > Signed-off-by: Klaus Jensen > --- > hw/block/nvme.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c > index bd7e258c3c26..40b9f8ccfc0e 100644 > --- a/hw/block/nvme.c > +++ b/hw/block/nvme.c > @@ -3781,19 +3781,21 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, > trace_pci_nvme_mmio_aqattr(data & 0xffffffff); > break; > case 0x28: /* ASQ */ > - n->bar.asq = data; > + n->bar.asq = size == 8 ? data : > + (n->bar.asq & ~0xffffffff) | (data & 0xffffffff); ^^^^^^^^^^^ If this one is to unmask lower 32bits other than higher 32bits, then it should be: (n->bar.asq & ~0xffffffffULL) Also, maybe we should take care of lower than 4bytes as: .min_access_size = 2, .max_access_size = 8, Even we have some error messages up there with: if (unlikely(size < sizeof(uint32_t))) { NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall, "MMIO write smaller than 32-bits," " offset=0x%"PRIx64", size=%u", offset, size); /* should be ignored, fall through for now */ } It's a fall-thru error, and that's it. I would prefer not to have this error and support for 2bytes access also, OR do not support for 2bytes access for this MMIO area. Thanks!