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From: Bin Meng <bmeng.cn@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	qemu-block@nongnu.org, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH v2 16/25] hw/sd: ssi-sd: Support single block write
Date: Sat, 23 Jan 2021 18:40:07 +0800	[thread overview]
Message-ID: <20210123104016.17485-17-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210123104016.17485-1-bmeng.cn@gmail.com>

From: Bin Meng <bin.meng@windriver.com>

Add 2 more states for the block write operation. The SPI host needs
to send a data start token to start the transfer, and the data block
written to the card will be acknowledged by a data response token.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>

---

Changes in v2:
- Correct the "token" typo in the commit message
- Add 'write_bytes' in vmstate_ssi_sd

 hw/sd/ssi-sd.c | 38 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
index 75e76cf87a..240cfd919c 100644
--- a/hw/sd/ssi-sd.c
+++ b/hw/sd/ssi-sd.c
@@ -43,6 +43,8 @@ typedef enum {
     SSI_SD_DATA_START,
     SSI_SD_DATA_READ,
     SSI_SD_DATA_CRC16,
+    SSI_SD_DATA_WRITE,
+    SSI_SD_SKIP_CRC16,
 } ssi_sd_mode;
 
 struct ssi_sd_state {
@@ -53,6 +55,7 @@ struct ssi_sd_state {
     uint8_t response[5];
     uint16_t crc16;
     int32_t read_bytes;
+    int32_t write_bytes;
     int32_t arglen;
     int32_t response_pos;
     int32_t stopping;
@@ -85,6 +88,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD)
 /* dummy value - don't care */
 #define SSI_DUMMY               0xff
 
+/* data accepted */
+#define DATA_RESPONSE_ACCEPTED  0x05
+
 static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val)
 {
     ssi_sd_state *s = SSI_SD(dev);
@@ -113,10 +119,17 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val)
 
     switch (s->mode) {
     case SSI_SD_CMD:
-        if (val == SSI_DUMMY) {
+        switch (val) {
+        case SSI_DUMMY:
             DPRINTF("NULL command\n");
             return SSI_DUMMY;
+            break;
+        case SSI_TOKEN_SINGLE:
+            DPRINTF("Start write block\n");
+            s->mode = SSI_SD_DATA_WRITE;
+            return SSI_DUMMY;
         }
+
         s->cmd = val & 0x3f;
         s->mode = SSI_SD_CMDARG;
         s->arglen = 0;
@@ -250,6 +263,27 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val)
             s->response_pos = 0;
         }
         return val;
+    case SSI_SD_DATA_WRITE:
+        sdbus_write_byte(&s->sdbus, val);
+        s->write_bytes++;
+        if (!sdbus_receive_ready(&s->sdbus) || s->write_bytes == 512) {
+            DPRINTF("Data write end\n");
+            s->mode = SSI_SD_SKIP_CRC16;
+            s->response_pos = 0;
+        }
+        return val;
+    case SSI_SD_SKIP_CRC16:
+        /* we don't verify the crc16 */
+        s->response_pos++;
+        if (s->response_pos == 2) {
+            DPRINTF("CRC16 receive end\n");
+            s->mode = SSI_SD_RESPONSE;
+            s->write_bytes = 0;
+            s->arglen = 1;
+            s->response[0] = DATA_RESPONSE_ACCEPTED;
+            s->response_pos = 0;
+        }
+        return SSI_DUMMY;
     }
     /* Should never happen.  */
     return SSI_DUMMY;
@@ -287,6 +321,7 @@ static const VMStateDescription vmstate_ssi_sd = {
         VMSTATE_UINT8_ARRAY(response, ssi_sd_state, 5),
         VMSTATE_UINT16(crc16, ssi_sd_state),
         VMSTATE_INT32(read_bytes, ssi_sd_state),
+        VMSTATE_INT32(write_bytes, ssi_sd_state),
         VMSTATE_INT32(arglen, ssi_sd_state),
         VMSTATE_INT32(response_pos, ssi_sd_state),
         VMSTATE_INT32(stopping, ssi_sd_state),
@@ -340,6 +375,7 @@ static void ssi_sd_reset(DeviceState *dev)
     memset(s->response, 0, sizeof(s->response));
     s->crc16 = 0;
     s->read_bytes = 0;
+    s->write_bytes = 0;
     s->arglen = 0;
     s->response_pos = 0;
     s->stopping = 0;
-- 
2.25.1



  parent reply	other threads:[~2021-01-23 11:02 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-23 10:39 [PATCH v2 00/25] hw/riscv: sifive_u: Add missing SPI support Bin Meng
2021-01-23 10:39 ` [PATCH v2 01/25] hw/block: m25p80: Add ISSI SPI flash support Bin Meng
2021-01-23 10:39 ` [PATCH v2 02/25] hw/block: m25p80: Add various ISSI flash information Bin Meng
2021-01-23 10:39 ` [PATCH v2 03/25] hw/sd: ssi-sd: Fix incorrect card response sequence Bin Meng
2021-01-24 17:48   ` Philippe Mathieu-Daudé
2021-01-23 10:39 ` [PATCH v2 04/25] hw/sd: sd: Support CMD59 for SPI mode Bin Meng
2021-01-24 17:21   ` Philippe Mathieu-Daudé
2021-01-23 10:39 ` [PATCH v2 05/25] hw/sd: sd: Drop sd_crc16() Bin Meng
2021-01-24 18:14   ` Philippe Mathieu-Daudé
2021-01-23 10:39 ` [PATCH v2 06/25] util: Add CRC16 (CCITT) calculation routines Bin Meng
2021-01-24 18:59   ` Philippe Mathieu-Daudé
2021-01-24 20:07     ` Richard Henderson
2021-01-24 20:24       ` Philippe Mathieu-Daudé
2021-01-24 21:41         ` Richard Henderson
2021-01-26  7:44           ` Philippe Mathieu-Daudé
2021-01-23 10:39 ` [PATCH v2 07/25] hw/sd: ssi-sd: Suffix a data block with CRC16 Bin Meng
2021-01-24 18:57   ` Philippe Mathieu-Daudé
2021-01-23 10:39 ` [PATCH v2 08/25] hw/sd: ssi-sd: Add a state representing Nac Bin Meng
2021-01-24 17:26   ` Philippe Mathieu-Daudé
2021-01-24 17:47   ` Philippe Mathieu-Daudé
2021-01-23 10:40 ` [PATCH v2 09/25] hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION Bin Meng
2021-01-24 17:33   ` Philippe Mathieu-Daudé
2021-01-24 17:35     ` Philippe Mathieu-Daudé
2021-01-25  0:33     ` Bin Meng
2021-01-25  0:42       ` Bin Meng
2021-01-23 10:40 ` [PATCH v2 10/25] hw/sd: ssi-sd: Support multiple block read Bin Meng
2021-01-23 10:40 ` [PATCH v2 11/25] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer Bin Meng
2021-01-24 17:36   ` Philippe Mathieu-Daudé
2021-01-23 10:40 ` [PATCH v2 12/25] hw/sd: sd: Remove duplicated codes in single/multiple block read/write Bin Meng
2021-01-23 10:40 ` [PATCH v2 13/25] hw/sd: sd: Allow single/multiple block write for SPI mode Bin Meng
2021-01-23 10:40 ` [PATCH v2 14/25] hw/sd: sd.h: Cosmetic change of using spaces Bin Meng
2021-01-24 17:43   ` Philippe Mathieu-Daudé
2021-01-23 10:40 ` [PATCH v2 15/25] hw/sd: Introduce receive_ready() callback Bin Meng
2021-01-23 10:40 ` Bin Meng [this message]
2021-01-23 10:40 ` [PATCH v2 17/25] hw/sd: ssi-sd: Support multiple block write Bin Meng
2021-01-23 10:40 ` [PATCH v2 18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription Bin Meng
2021-01-24 16:59   ` Philippe Mathieu-Daudé
2021-01-24 17:07     ` Philippe Mathieu-Daudé
2021-01-25  1:20     ` Bin Meng
2021-01-25 10:41       ` Dr. David Alan Gilbert
2021-01-25 10:48         ` Bin Meng
2021-01-23 10:40 ` [PATCH v2 19/25] hw/ssi: Add SiFive SPI controller support Bin Meng
2021-01-23 10:40 ` [PATCH v2 20/25] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash Bin Meng
2021-01-23 10:40 ` [PATCH v2 21/25] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card Bin Meng
2021-01-23 10:40 ` [PATCH v2 22/25] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value Bin Meng
2021-01-23 10:40 ` [PATCH v2 23/25] docs/system: Sort targets in alphabetical order Bin Meng
2021-01-23 10:40 ` [PATCH v2 24/25] docs/system: Add RISC-V documentation Bin Meng
2021-01-23 10:40 ` [PATCH v2 25/25] docs/system: riscv: Add documentation for sifive_u machine Bin Meng
2021-01-24 20:07 ` [PATCH v2 00/25] hw/riscv: sifive_u: Add missing SPI support Philippe Mathieu-Daudé

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