From: michael.nawrocki--- via <qemu-devel@nongnu.org>
To: <qemu-arm@nongnu.org>
Cc: qemu-trivial@nongnu.org, peter.maydell@linaro.org,
qemu-devel@nongnu.org,
Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
Subject: [PATCH 1/1] target/arm: Add raw_writefn to SCR_EL3 register
Date: Thu, 28 Jan 2021 09:31:02 -0500 [thread overview]
Message-ID: <20210128143102.7834-2-michael.nawrocki@gtri.gatech.edu> (raw)
In-Reply-To: <20210128143102.7834-1-michael.nawrocki@gtri.gatech.edu>
Fixes an issue in migration where the reset value of SCR and the value
produced by scr_write via the writefn for SCR_EL3 mismatch.
Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2ead3fcbd..e3c4fe76cb 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5785,7 +5785,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
- .resetvalue = 0, .writefn = scr_write },
+ .resetvalue = 0, .writefn = scr_write, .raw_writefn = raw_write },
{ .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
--
2.20.1
next prev parent reply other threads:[~2021-01-28 14:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-28 14:31 [PATCH 0/1] target/arm: Fix SCR_EL3 migration issue michael.nawrocki--- via
2021-01-28 14:31 ` michael.nawrocki--- via [this message]
2021-02-02 11:29 ` [PATCH 1/1] target/arm: Add raw_writefn to SCR_EL3 register Peter Maydell
2021-02-03 14:50 ` michael.nawrocki--- via
2021-02-03 15:04 ` Peter Maydell
2021-02-03 16:58 ` michael.nawrocki--- via
2021-01-28 14:38 ` [PATCH 0/1] target/arm: Fix SCR_EL3 migration issue Peter Maydell
2021-02-03 16:28 ` Philippe Mathieu-Daudé
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