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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id j6sm8857259pfg.159.2021.01.29.05.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 05:23:46 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Fri, 29 Jan 2021 21:23:13 +0800 Message-Id: <20210129132323.30946-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Starting from v8, the series is based on the following 2 versions: - v5 series sent from Bin http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919 - v7 series sent from Philippe http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612 This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - remove imx_spi_update_irq() in imx_spi_reset() - chip select signal was not lower down when spi controller is disabled - round up the tx burst length to be multiple of 8 - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect - remove pointless variable (s->burst_length) initialization (Philippe) - rework imx_spi_reset() to keep CONREG register value (Philippe) - rework imx_spi_read() to handle block disabled (Philippe) - rework imx_spi_write() to handle block disabled (Philippe) Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 (interrupt mode). Changes in v9: - Add a 'common_reset' function that does most of reset operation, leaving ECSPI_CONREG clear in imx_spi_reset(). - Do the LOG_UNIMP when the unsupported burst length value is written, rather than where it is used. - Squash the 2 LOG_UNIMP warnings down into one line Changes in v8: - keep the controller disable logic in the ECSPI_CONREG case in imx_spi_write() Changes in v7: - remove the RFC tag - remove the RFC tag - remove the RFC tag - remove the RFC tag Changes in v6: - new patch: [RFC] remove pointless variable initialization - new patch: [RFC] rework imx_spi_reset() to keep CONREG register value - new patch: [RFC] rework imx_spi_read() to handle block disabled - new patch: [RFC] rework imx_spi_write() to handle block disabled Changes in v5: - rename imx_spi_hard_reset() to imx_spi_soft_reset() - round up the burst length to be multiple of 8 Changes in v4: - adujst the patch 2,3 order - rename imx_spi_soft_reset() to imx_spi_hard_reset() to avoid confusion - s/normal/common/ in the commit message - log the burst length value in the log message Changes in v3: - new patch: remove imx_spi_update_irq() in imx_spi_reset() - Move the chip selects disable out of imx_spi_reset() - new patch: log unimplemented burst length - Simplify the tx fifo endianness handling Changes in v2: - Fix the "Fixes" tag in the commit message - Use ternary operator as Philippe suggested Bin Meng (5): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Round up the burst length to be multiple of 8 hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Philippe Mathieu-Daudé (4): hw/ssi: imx_spi: Remove pointless variable initialization hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects when controller is disabled include/hw/ssi/imx_spi.h | 5 +- hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++-------------- 2 files changed, 101 insertions(+), 57 deletions(-) -- 2.25.1