From: Bin Meng <bmeng.cn@gmail.com>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Jean-Christophe Dubois" <jcd@tribudubois.net>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>, Juan Quintela <quintela@redhat.com>
Subject: [PATCH v9 01/10] hw/ssi: imx_spi: Use a macro for number of chip selects supported
Date: Fri, 29 Jan 2021 21:23:14 +0800 [thread overview]
Message-ID: <20210129132323.30946-2-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
Avoid using a magic number (4) everywhere for the number of chip
selects supported.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
---
(no changes since v1)
include/hw/ssi/imx_spi.h | 5 ++++-
hw/ssi/imx_spi.c | 4 ++--
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/include/hw/ssi/imx_spi.h b/include/hw/ssi/imx_spi.h
index b82b17f364..eeaf49bbac 100644
--- a/include/hw/ssi/imx_spi.h
+++ b/include/hw/ssi/imx_spi.h
@@ -77,6 +77,9 @@
#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
+/* number of chip selects supported */
+#define ECSPI_NUM_CS 4
+
#define TYPE_IMX_SPI "imx.spi"
OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI)
@@ -89,7 +92,7 @@ struct IMXSPIState {
qemu_irq irq;
- qemu_irq cs_lines[4];
+ qemu_irq cs_lines[ECSPI_NUM_CS];
SSIBus *bus;
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index d8885ae454..e605049a21 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -361,7 +361,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
/* We are in master mode */
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
qemu_set_irq(s->cs_lines[i],
i == imx_spi_selected_channel(s) ? 0 : 1);
}
@@ -424,7 +424,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
- for (i = 0; i < 4; ++i) {
+ for (i = 0; i < ECSPI_NUM_CS; ++i) {
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
}
--
2.25.1
next prev parent reply other threads:[~2021-01-29 13:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-29 13:23 [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-29 13:23 ` Bin Meng [this message]
2021-01-29 13:23 ` [PATCH v9 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Bin Meng
2021-01-29 13:23 ` [PATCH v9 03/10] hw/ssi: imx_spi: Remove pointless variable initialization Bin Meng
2021-01-29 13:23 ` [PATCH v9 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Bin Meng
2021-01-29 14:00 ` Philippe Mathieu-Daudé
2021-01-29 13:23 ` [PATCH v9 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Bin Meng
2021-01-29 13:23 ` [PATCH v9 06/10] hw/ssi: imx_spi: Rework imx_spi_write() " Bin Meng
2021-01-29 13:23 ` [PATCH v9 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled Bin Meng
2021-01-29 13:23 ` [PATCH v9 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Bin Meng
2021-01-29 13:23 ` [PATCH v9 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Bin Meng
2021-01-29 13:23 ` [PATCH v9 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness Bin Meng
2021-02-02 11:39 ` [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Peter Maydell
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