From: Bin Meng <bmeng.cn@gmail.com>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Jean-Christophe Dubois" <jcd@tribudubois.net>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Xuzhou Cheng <xuzhou.cheng@windriver.com>,
Bin Meng <bin.meng@windriver.com>
Subject: [PATCH v9 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled
Date: Fri, 29 Jan 2021 21:23:20 +0800 [thread overview]
Message-ID: <20210129132323.30946-8-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com>
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_soft_reset() is called to reset the controller, but chip
select lines should have been disabled, otherwise the state machine
of any devices (e.g.: SPI flashes) connected to the SPI master is
stuck to its last state and responds incorrectly to any follow-up
commands.
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
(no changes since v3)
Changes in v3:
- Move the chip selects disable out of imx_spi_reset()
Changes in v2:
- Fix the "Fixes" tag in the commit message
hw/ssi/imx_spi.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 4cfbb73e35..2fb65498c3 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -254,9 +254,15 @@ static void imx_spi_common_reset(IMXSPIState *s)
static void imx_spi_soft_reset(IMXSPIState *s)
{
+ int i;
+
imx_spi_common_reset(s);
imx_spi_update_irq(s);
+
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
+ qemu_set_irq(s->cs_lines[i], 1);
+ }
}
static void imx_spi_reset(DeviceState *dev)
--
2.25.1
next prev parent reply other threads:[~2021-01-29 13:38 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-29 13:23 [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-29 13:23 ` [PATCH v9 01/10] hw/ssi: imx_spi: Use a macro for number of chip selects supported Bin Meng
2021-01-29 13:23 ` [PATCH v9 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Bin Meng
2021-01-29 13:23 ` [PATCH v9 03/10] hw/ssi: imx_spi: Remove pointless variable initialization Bin Meng
2021-01-29 13:23 ` [PATCH v9 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Bin Meng
2021-01-29 14:00 ` Philippe Mathieu-Daudé
2021-01-29 13:23 ` [PATCH v9 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Bin Meng
2021-01-29 13:23 ` [PATCH v9 06/10] hw/ssi: imx_spi: Rework imx_spi_write() " Bin Meng
2021-01-29 13:23 ` Bin Meng [this message]
2021-01-29 13:23 ` [PATCH v9 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Bin Meng
2021-01-29 13:23 ` [PATCH v9 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Bin Meng
2021-01-29 13:23 ` [PATCH v9 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness Bin Meng
2021-02-02 11:39 ` [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Peter Maydell
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