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From: Leif Lindholm <leif@nuviainc.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Shashi Mallela <shashi.mallela@linaro.org>,
	qemu-arm <qemu-arm@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [RFC PATCH 4/4] hw/intc: make gicv3_idreg() distinguish between gicv3/gicv4
Date: Wed, 3 Feb 2021 11:36:17 +0000	[thread overview]
Message-ID: <20210203113617.GV1664@vanye> (raw)
In-Reply-To: <CAFEAcA-j8TeozQLSTSK1ueVFKZ4J6tTCjMBNJMQTLQCeAnKkpw@mail.gmail.com>

On Tue, Feb 02, 2021 at 10:31:16 +0000, Peter Maydell wrote:
> On Sun, 24 Jan 2021 at 02:53, Leif Lindholm <leif@nuviainc.com> wrote:
> >
> > Make gicv3_idreg() able to return either gicv3 or gicv4 data.
> > Add a parameter to specify gic version.
> >
> > Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> > ---
> >  hw/intc/arm_gicv3_dist.c   |  2 +-
> >  hw/intc/arm_gicv3_redist.c |  2 +-
> >  hw/intc/gicv3_internal.h   | 12 ++++++++++--
> >  3 files changed, 12 insertions(+), 4 deletions(-)
> 
> > -static inline uint32_t gicv3_idreg(int regoffset)
> > +static inline uint32_t gicv3_idreg(int regoffset, int revision)
> 
> I would prefer to pass in the GICv3State* and let the function
> look at s->revision.

Yeah, that'd be neater.

> >  {
> >      /* Return the value of the CoreSight ID register at the specified
> >       * offset from the first ID register (as found in the distributor
> > @@ -331,7 +331,15 @@ static inline uint32_t gicv3_idreg(int regoffset)
> >      static const uint8_t gicd_ids[] = {
> >          0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1
> >      };
> > -    return gicd_ids[regoffset / 4];
> > +    static const uint8_t gicdv4_ids[] = {
> > +        0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x4B, 0x00, 0x0D, 0xF0, 0x05, 0xB1
> > +    };
> > +
> > +    if (revision == 3) {
> > +        return gicd_ids[regoffset / 4];
> > +    } else {
> > +        return gicdv4_ids[regoffset / 4];
> > +    }
> >  }
> 
> Updating the comment "These values indicate an ARM implementation of a GICv3"
> to add a note about what the new values are indicating would be nice.

Will do.

Regards,

Leif


  reply	other threads:[~2021-02-03 11:40 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-24  2:53 [RFC PATCH 0/4] hw/intc: enable GICv4 memory layout for GICv3 driver Leif Lindholm
2021-01-24  2:53 ` [RFC PATCH 1/4] hw/intc: don't bail out gicv3 model init for revision 4 Leif Lindholm
2021-02-02 10:34   ` Peter Maydell
2021-01-24  2:53 ` [RFC PATCH 2/4] hw/intc: add helper function to determine gicv3 redistributor size Leif Lindholm
2021-02-02 10:27   ` Peter Maydell
2021-01-24  2:53 ` [RFC PATCH 3/4] hw/intc: set GICD_TYPER.DVIS for GICv4 Leif Lindholm
2021-02-02 10:34   ` Peter Maydell
2021-01-24  2:53 ` [RFC PATCH 4/4] hw/intc: make gicv3_idreg() distinguish between gicv3/gicv4 Leif Lindholm
2021-02-02 10:31   ` Peter Maydell
2021-02-03 11:36     ` Leif Lindholm [this message]
2021-01-24  3:00 ` [RFC PATCH 0/4] hw/intc: enable GICv4 memory layout for GICv3 driver no-reply
2021-02-02 10:39 ` Peter Maydell
2021-02-03 12:26   ` Leif Lindholm

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