From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: sw@weilnetz.de, "Alex Bennée" <alex.bennee@linaro.org>
Subject: [PATCH v2 12/93] tcg/tci: Inline tci_write_reg64 into 64-bit callers
Date: Wed, 3 Feb 2021 15:43:48 -1000 [thread overview]
Message-ID: <20210204014509.882821-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210204014509.882821-1-richard.henderson@linaro.org>
Note that we had two functions of the same name: a 32-bit version
which took two register numbers and a 64-bit version which was a
no-op wrapper for tcg_write_reg. After this, we are left with
only the 32-bit version.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 60 +++++++++++++++++++++++++------------------------------
1 file changed, 27 insertions(+), 33 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 39ad00663f..0f56702b93 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -124,12 +124,6 @@ static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
tci_write_reg(regs, low_index, value);
tci_write_reg(regs, high_index, value >> 32);
}
-#elif TCG_TARGET_REG_BITS == 64
-static void
-tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value)
-{
- tci_write_reg(regs, index, value);
-}
#endif
#if TCG_TARGET_REG_BITS == 32
@@ -559,7 +553,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t1 = tci_read_r64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
condition = *tb_ptr++;
- tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition));
+ tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break;
#endif
case INDEX_op_mov_i32:
@@ -839,12 +833,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_mov_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i64:
t0 = *tb_ptr++;
t1 = tci_read_i64(&tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
/* Load/store operations (64 bit). */
@@ -886,7 +880,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2));
+ tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st8_i64:
t0 = tci_read_r8(regs, &tb_ptr);
@@ -920,19 +914,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 + t2);
+ tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 - t2);
+ tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 * t2);
+ tci_write_reg(regs, t0, t1 * t2);
break;
#if TCG_TARGET_HAS_div_i64
case INDEX_op_div_i64:
@@ -951,19 +945,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 & t2);
+ tci_write_reg(regs, t0, t1 & t2);
break;
case INDEX_op_or_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 | t2);
+ tci_write_reg(regs, t0, t1 | t2);
break;
case INDEX_op_xor_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 ^ t2);
+ tci_write_reg(regs, t0, t1 ^ t2);
break;
/* Shift/rotate operations (64 bit). */
@@ -972,32 +966,32 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 << (t2 & 63));
+ tci_write_reg(regs, t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 >> (t2 & 63));
+ tci_write_reg(regs, t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63)));
+ tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, rol64(t1, t2 & 63));
+ tci_write_reg(regs, t0, rol64(t1, t2 & 63));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, ror64(t1, t2 & 63));
+ tci_write_reg(regs, t0, ror64(t1, t2 & 63));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
@@ -1008,7 +1002,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
- tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
+ tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
break;
#endif
case INDEX_op_brcond_i64:
@@ -1026,28 +1020,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ext8u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r8(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext8s_i64
case INDEX_op_ext8s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r8s(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i64
case INDEX_op_ext16s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16s(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i64
case INDEX_op_ext16u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext32s_i64
@@ -1056,7 +1050,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ext_i32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32s(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#if TCG_TARGET_HAS_ext32u_i64
case INDEX_op_ext32u_i64:
@@ -1064,41 +1058,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_extu_i32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#if TCG_TARGET_HAS_bswap16_i64
case INDEX_op_bswap16_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16(regs, &tb_ptr);
- tci_write_reg64(regs, t0, bswap16(t1));
+ tci_write_reg(regs, t0, bswap16(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap32_i64
case INDEX_op_bswap32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg64(regs, t0, bswap32(t1));
+ tci_write_reg(regs, t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, bswap64(t1));
+ tci_write_reg(regs, t0, bswap64(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i64
case INDEX_op_not_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, ~t1);
+ tci_write_reg(regs, t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i64
case INDEX_op_neg_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, -t1);
+ tci_write_reg(regs, t0, -t1);
break;
#endif
#endif /* TCG_TARGET_REG_BITS == 64 */
--
2.25.1
next prev parent reply other threads:[~2021-02-04 1:51 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-04 1:43 [PATCH v2 00/93] TCI fixes and cleanups Richard Henderson
2021-02-04 1:43 ` [PATCH v2 01/93] gdbstub: Fix handle_query_xfer_auxv Richard Henderson
2021-02-04 1:43 ` [PATCH v2 02/93] tcg: Split out tcg_raise_tb_overflow Richard Henderson
2021-02-04 1:43 ` [PATCH v2 03/93] configure: Fix --enable-tcg-interpreter Richard Henderson
2021-02-04 1:43 ` [PATCH v2 04/93] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Richard Henderson
2021-02-04 15:01 ` Alex Bennée
2021-02-04 17:46 ` Richard Henderson
2021-02-04 18:45 ` Alex Bennée
2021-02-04 19:17 ` Richard Henderson
2021-02-04 1:43 ` [PATCH v2 05/93] tcg/tci: Make tci_tb_ptr thread-local Richard Henderson
2021-02-04 15:05 ` Alex Bennée
2021-02-04 1:43 ` [PATCH v2 06/93] tcg/tci: Implement INDEX_op_ld16s_i32 Richard Henderson
2021-02-04 1:43 ` [PATCH v2 07/93] tcg/tci: Implement INDEX_op_ld8s_i64 Richard Henderson
2021-02-04 1:43 ` [PATCH v2 08/93] tcg/tci: Inline tci_write_reg32s into the only caller Richard Henderson
2021-02-04 1:43 ` [PATCH v2 09/93] tcg/tci: Inline tci_write_reg8 into its callers Richard Henderson
2021-02-04 1:43 ` [PATCH v2 10/93] tcg/tci: Inline tci_write_reg16 into the only caller Richard Henderson
2021-02-04 1:43 ` [PATCH v2 11/93] tcg/tci: Inline tci_write_reg32 into all callers Richard Henderson
2021-02-04 1:43 ` Richard Henderson [this message]
2021-02-04 1:43 ` [PATCH v2 13/93] tcg/tci: Merge INDEX_op_ld8u_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 14/93] tcg/tci: Merge INDEX_op_ld8s_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 15/93] tcg/tci: Merge INDEX_op_ld16u_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 16/93] tcg/tci: Merge INDEX_op_ld16s_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 17/93] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 18/93] tcg/tci: Merge INDEX_op_st8_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 19/93] tcg/tci: Merge INDEX_op_st16_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 20/93] tcg/tci: Move stack bounds check to compile-time Richard Henderson
2021-02-04 1:43 ` [PATCH v2 21/93] tcg/tci: Merge INDEX_op_{st_i32,st32_i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 22/93] tcg/tci: Use g_assert_not_reached Richard Henderson
2021-02-04 1:43 ` [PATCH v2 23/93] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* Richard Henderson
2021-02-04 1:44 ` [PATCH v2 24/93] tcg/tci: Implement 64-bit division Richard Henderson
2021-02-04 1:44 ` [PATCH v2 25/93] tcg/tci: Remove TODO as unused Richard Henderson
2021-02-04 1:44 ` [PATCH v2 26/93] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 Richard Henderson
2021-02-04 15:07 ` Alex Bennée
2021-02-04 1:44 ` [PATCH v2 27/93] tcg/tci: Fix TCG_REG_R4 misusage Richard Henderson
2021-02-04 15:09 ` Alex Bennée
2021-02-04 1:44 ` [PATCH v2 28/93] tcg/tci: Use bool in tcg_out_ri* Richard Henderson
2021-02-04 15:11 ` Alex Bennée
2021-02-04 15:15 ` Alex Bennée
2021-02-04 1:44 ` [PATCH v2 29/93] tcg/tci: Remove TCG_CONST Richard Henderson
2021-02-04 15:39 ` Alex Bennée
2021-02-04 17:52 ` Richard Henderson
2021-02-04 18:48 ` Alex Bennée
2021-02-04 1:44 ` [PATCH v2 30/93] tcg/tci: Merge identical cases in generation Richard Henderson
2021-02-04 1:44 ` [PATCH v2 31/93] tcg/tci: Remove tci_read_r8 Richard Henderson
2021-02-04 1:44 ` [PATCH v2 32/93] tcg/tci: Remove tci_read_r8s Richard Henderson
2021-02-04 1:44 ` [PATCH v2 33/93] tcg/tci: Remove tci_read_r16 Richard Henderson
2021-02-04 1:44 ` [PATCH v2 34/93] tcg/tci: Remove tci_read_r16s Richard Henderson
2021-02-04 1:44 ` [PATCH v2 35/93] tcg/tci: Remove tci_read_r32s Richard Henderson
2021-02-04 1:44 ` [PATCH v2 36/93] tcg/tci: Reduce use of tci_read_r64 Richard Henderson
2021-02-04 1:44 ` [PATCH v2 37/93] tcg/tci: Merge basic arithmetic operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 38/93] tcg/tci: Merge extension operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 39/93] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
2021-02-04 1:44 ` [PATCH v2 40/93] tcg/tci: Merge bswap operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 41/93] tcg/tci: Merge mov, not and neg operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 42/93] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
2021-02-04 1:44 ` [PATCH v2 43/93] tcg/tci: Split out tci_args_rrs Richard Henderson
2021-02-04 1:44 ` [PATCH v2 44/93] tcg/tci: Split out tci_args_rr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 45/93] tcg/tci: Split out tci_args_rrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 46/93] tcg/tci: Split out tci_args_rrrc Richard Henderson
2021-02-04 1:44 ` [PATCH v2 47/93] tcg/tci: Split out tci_args_l Richard Henderson
2021-02-04 1:44 ` [PATCH v2 48/93] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
2021-02-04 1:44 ` [PATCH v2 49/93] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
2021-02-04 1:44 ` [PATCH v2 50/93] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
2021-02-04 1:44 ` [PATCH v2 51/93] tcg/tci: Reuse tci_args_l for calls Richard Henderson
2021-02-04 1:44 ` [PATCH v2 52/93] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
2021-02-04 1:44 ` [PATCH v2 53/93] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
2021-02-04 1:44 ` [PATCH v2 54/93] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 55/93] tcg/tci: Split out tci_args_rrrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 56/93] tcg/tci: Clean up deposit operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 57/93] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
2021-02-04 1:44 ` [PATCH v2 58/93] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-04 1:44 ` [PATCH v2 59/93] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
2021-02-04 1:44 ` [PATCH v2 60/93] tcg/tci: Remove tci_disas Richard Henderson
2021-02-04 1:44 ` [PATCH v2 61/93] tcg/tci: Implement the disassembler properly Richard Henderson
2021-02-04 1:44 ` [PATCH v2 62/93] tcg: Build ffi data structures for helpers Richard Henderson
2021-02-04 1:44 ` [PATCH v2 63/93] tcg/tci: Use ffi for calls Richard Henderson
2021-02-07 16:25 ` Stefan Weil
2021-02-07 17:39 ` Richard Henderson
2021-02-07 19:52 ` Peter Maydell
2021-02-07 20:12 ` Richard Henderson
2021-02-07 21:33 ` Stefan Weil
2021-02-08 9:20 ` Peter Maydell
2021-02-08 9:35 ` Paolo Bonzini
2021-02-08 13:07 ` Stefan Weil
2021-02-08 17:39 ` Richard Henderson
2021-02-08 19:04 ` Stefan Weil
2021-02-08 22:55 ` Richard Henderson
2021-02-09 20:46 ` Richard Henderson
2021-02-09 21:15 ` Stefan Weil
2021-02-09 21:54 ` Stefan Weil
2021-02-04 1:44 ` [PATCH v2 64/93] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-02-04 1:44 ` [PATCH v2 65/93] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-02-04 1:44 ` [PATCH v2 66/93] tcg/tci: Push opcode emit into each case Richard Henderson
2021-02-04 1:44 ` [PATCH v2 67/93] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
2021-02-04 1:44 ` [PATCH v2 68/93] tcg/tci: Split out tcg_out_op_l Richard Henderson
2021-02-04 1:44 ` [PATCH v2 69/93] tcg/tci: Split out tcg_out_op_p Richard Henderson
2021-02-04 1:44 ` [PATCH v2 70/93] tcg/tci: Split out tcg_out_op_rr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 71/93] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 72/93] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
2021-02-04 1:44 ` [PATCH v2 73/93] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
2021-02-04 1:44 ` [PATCH v2 74/93] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
2021-02-04 1:44 ` [PATCH v2 75/93] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
2021-02-04 1:44 ` [PATCH v2 76/93] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 77/93] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 78/93] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
2021-02-04 1:44 ` [PATCH v2 79/93] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-04 1:54 ` Richard Henderson
2021-02-04 14:54 ` Alex Bennée
2021-02-04 17:54 ` Richard Henderson
2021-02-04 1:54 ` [PATCH v2 80/93] tcg/tci: Split out tcg_out_op_v Richard Henderson
2021-02-04 1:55 ` [PATCH v2 81/93] tcg/tci: Split out tcg_out_op_np Richard Henderson
2021-02-04 1:55 ` [PATCH v2 82/93] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
2021-02-04 1:55 ` [PATCH v2 83/93] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-02-04 1:56 ` [PATCH v2 84/93] tcg/tci: Emit setcond before brcond Richard Henderson
2021-02-04 1:56 ` [PATCH v2 85/93] tcg/tci: Remove tci_write_reg Richard Henderson
2021-02-04 1:56 ` [PATCH v2 86/93] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-02-04 1:57 ` [PATCH v2 87/93] tcg/tci: Implement goto_ptr Richard Henderson
2021-02-04 1:57 ` [PATCH v2 88/93] tcg/tci: Implement movcond Richard Henderson
2021-02-04 1:57 ` [PATCH v2 89/93] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-02-04 1:57 ` [PATCH v2 90/93] tcg/tci: Implement extract, sextract Richard Henderson
2021-02-04 1:58 ` [PATCH v2 91/93] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-02-04 1:58 ` [PATCH v2 92/93] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-02-04 1:58 ` [PATCH v2 93/93] tcg/tci: Implement add2, sub2 Richard Henderson
2021-02-04 3:31 ` [PATCH v2 00/93] TCI fixes and cleanups no-reply
2021-02-04 9:58 ` Peter Maydell
2021-02-04 20:02 ` Stefan Weil
2021-02-04 20:42 ` Richard Henderson
2021-02-04 23:52 ` Richard Henderson
2021-02-05 2:39 ` Richard Henderson
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