From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Claudio Fontana" <cfontana@suse.de>
Subject: [PULL 40/46] physmem: make watchpoint checking code TCG-only
Date: Fri, 5 Feb 2021 12:56:44 -1000 [thread overview]
Message-ID: <20210205225650.1330794-41-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210205225650.1330794-1-richard.henderson@linaro.org>
From: Claudio Fontana <cfontana@suse.de>
cpu_check_watchpoint, watchpoint_address_matches are TCG-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-13-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
softmmu/physmem.c | 141 +++++++++++++++++++++++-----------------------
1 file changed, 72 insertions(+), 69 deletions(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 60760a3bdc..51ed600bf9 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -840,6 +840,7 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
}
}
+#ifdef CONFIG_TCG
/* Return true if this watchpoint address matches the specified
* access (ie the address range covered by the watchpoint overlaps
* partially or completely with the address range covered by the
@@ -873,6 +874,77 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
return ret;
}
+/* Generate a debug exception if a watchpoint has been hit. */
+void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
+ MemTxAttrs attrs, int flags, uintptr_t ra)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ CPUWatchpoint *wp;
+
+ assert(tcg_enabled());
+ if (cpu->watchpoint_hit) {
+ /*
+ * We re-entered the check after replacing the TB.
+ * Now raise the debug interrupt so that it will
+ * trigger after the current instruction.
+ */
+ qemu_mutex_lock_iothread();
+ cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
+ qemu_mutex_unlock_iothread();
+ return;
+ }
+
+ addr = cc->adjust_watchpoint_address(cpu, addr, len);
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
+ if (watchpoint_address_matches(wp, addr, len)
+ && (wp->flags & flags)) {
+ if (replay_running_debug()) {
+ /*
+ * Don't process the watchpoints when we are
+ * in a reverse debugging operation.
+ */
+ replay_breakpoint();
+ return;
+ }
+ if (flags == BP_MEM_READ) {
+ wp->flags |= BP_WATCHPOINT_HIT_READ;
+ } else {
+ wp->flags |= BP_WATCHPOINT_HIT_WRITE;
+ }
+ wp->hitaddr = MAX(addr, wp->vaddr);
+ wp->hitattrs = attrs;
+ if (!cpu->watchpoint_hit) {
+ if (wp->flags & BP_CPU &&
+ !cc->debug_check_watchpoint(cpu, wp)) {
+ wp->flags &= ~BP_WATCHPOINT_HIT;
+ continue;
+ }
+ cpu->watchpoint_hit = wp;
+
+ mmap_lock();
+ tb_check_watchpoint(cpu, ra);
+ if (wp->flags & BP_STOP_BEFORE_ACCESS) {
+ cpu->exception_index = EXCP_DEBUG;
+ mmap_unlock();
+ cpu_loop_exit_restore(cpu, ra);
+ } else {
+ /* Force execution of one insn next time. */
+ cpu->cflags_next_tb = 1 | curr_cflags();
+ mmap_unlock();
+ if (ra) {
+ cpu_restore_state(cpu, ra, true);
+ }
+ cpu_loop_exit_noexc(cpu);
+ }
+ }
+ } else {
+ wp->flags &= ~BP_WATCHPOINT_HIT;
+ }
+ }
+}
+
+#endif /* CONFIG_TCG */
+
/* Called from RCU critical section */
static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
{
@@ -2359,75 +2431,6 @@ ram_addr_t qemu_ram_addr_from_host(void *ptr)
return block->offset + offset;
}
-/* Generate a debug exception if a watchpoint has been hit. */
-void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs attrs, int flags, uintptr_t ra)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUWatchpoint *wp;
-
- assert(tcg_enabled());
- if (cpu->watchpoint_hit) {
- /*
- * We re-entered the check after replacing the TB.
- * Now raise the debug interrupt so that it will
- * trigger after the current instruction.
- */
- qemu_mutex_lock_iothread();
- cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
- qemu_mutex_unlock_iothread();
- return;
- }
-
- addr = cc->adjust_watchpoint_address(cpu, addr, len);
- QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- if (watchpoint_address_matches(wp, addr, len)
- && (wp->flags & flags)) {
- if (replay_running_debug()) {
- /*
- * Don't process the watchpoints when we are
- * in a reverse debugging operation.
- */
- replay_breakpoint();
- return;
- }
- if (flags == BP_MEM_READ) {
- wp->flags |= BP_WATCHPOINT_HIT_READ;
- } else {
- wp->flags |= BP_WATCHPOINT_HIT_WRITE;
- }
- wp->hitaddr = MAX(addr, wp->vaddr);
- wp->hitattrs = attrs;
- if (!cpu->watchpoint_hit) {
- if (wp->flags & BP_CPU &&
- !cc->debug_check_watchpoint(cpu, wp)) {
- wp->flags &= ~BP_WATCHPOINT_HIT;
- continue;
- }
- cpu->watchpoint_hit = wp;
-
- mmap_lock();
- tb_check_watchpoint(cpu, ra);
- if (wp->flags & BP_STOP_BEFORE_ACCESS) {
- cpu->exception_index = EXCP_DEBUG;
- mmap_unlock();
- cpu_loop_exit_restore(cpu, ra);
- } else {
- /* Force execution of one insn next time. */
- cpu->cflags_next_tb = 1 | curr_cflags();
- mmap_unlock();
- if (ra) {
- cpu_restore_state(cpu, ra, true);
- }
- cpu_loop_exit_noexc(cpu);
- }
- }
- } else {
- wp->flags &= ~BP_WATCHPOINT_HIT;
- }
- }
-}
-
static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
MemTxAttrs attrs, void *buf, hwaddr len);
static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
--
2.25.1
next prev parent reply other threads:[~2021-02-05 23:30 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
2021-02-05 22:56 ` [PULL 01/46] tcg/s390: Fix compare instruction from extended-immediate facility Richard Henderson
2021-02-05 22:56 ` [PULL 02/46] exec/cpu-defs: Remove TCG backends dependency Richard Henderson
2021-02-05 22:56 ` [PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps Richard Henderson
2021-02-05 22:56 ` [PULL 04/46] configure: Fix --enable-tcg-interpreter Richard Henderson
2021-02-05 22:56 ` [PULL 05/46] tcg/tci: Make tci_tb_ptr thread-local Richard Henderson
2021-02-05 22:56 ` [PULL 06/46] tcg/tci: Implement INDEX_op_ld16s_i32 Richard Henderson
2021-02-05 22:56 ` [PULL 07/46] tcg/tci: Implement INDEX_op_ld8s_i64 Richard Henderson
2021-02-05 22:56 ` [PULL 08/46] tcg/tci: Inline tci_write_reg32s into the only caller Richard Henderson
2021-02-05 22:56 ` [PULL 09/46] tcg/tci: Inline tci_write_reg8 into its callers Richard Henderson
2021-02-05 22:56 ` [PULL 10/46] tcg/tci: Inline tci_write_reg16 into the only caller Richard Henderson
2021-02-05 22:56 ` [PULL 11/46] tcg/tci: Inline tci_write_reg32 into all callers Richard Henderson
2021-02-05 22:56 ` [PULL 12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers Richard Henderson
2021-02-05 22:56 ` [PULL 13/46] tcg/tci: Merge INDEX_op_ld8u_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 15/46] tcg/tci: Merge INDEX_op_ld16u_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 16/46] tcg/tci: Merge INDEX_op_ld16s_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 17/46] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64} Richard Henderson
2021-02-05 22:56 ` [PULL 18/46] tcg/tci: Merge INDEX_op_st8_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 19/46] tcg/tci: Merge INDEX_op_st16_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 20/46] tcg/tci: Move stack bounds check to compile-time Richard Henderson
2021-02-05 22:56 ` [PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64} Richard Henderson
2021-02-05 22:56 ` [PULL 22/46] tcg/tci: Use g_assert_not_reached Richard Henderson
2021-02-05 22:56 ` [PULL 23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* Richard Henderson
2021-02-05 22:56 ` [PULL 24/46] tcg/tci: Implement 64-bit division Richard Henderson
2021-02-05 22:56 ` [PULL 25/46] tcg/tci: Remove TODO as unused Richard Henderson
2021-02-05 22:56 ` [PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 Richard Henderson
2021-02-05 22:56 ` [PULL 27/46] tcg/tci: Fix TCG_REG_R4 misusage Richard Henderson
2021-02-05 22:56 ` [PULL 28/46] tcg/tci: Remove TCG_CONST Richard Henderson
2021-02-05 22:56 ` [PULL 29/46] cpu: Introduce TCGCpuOperations struct Richard Henderson
2021-02-05 22:56 ` [PULL 30/46] target/riscv: remove CONFIG_TCG, as it is always TCG Richard Henderson
2021-02-05 22:56 ` [PULL 31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn Richard Henderson
2021-02-05 22:56 ` [PULL 32/46] cpu: Move synchronize_from_tb() to tcg_ops Richard Henderson
2021-02-05 22:56 ` [PULL 33/46] cpu: Move cpu_exec_* " Richard Henderson
2021-02-05 22:56 ` [PULL 34/46] cpu: Move tlb_fill " Richard Henderson
2021-02-05 22:56 ` [PULL 35/46] cpu: Move debug_excp_handler " Richard Henderson
2021-02-05 22:56 ` [PULL 36/46] target/arm: do not use cc->do_interrupt for KVM directly Richard Henderson
2021-02-05 22:56 ` [PULL 37/46] cpu: move cc->do_interrupt to tcg_ops Richard Henderson
2021-02-05 22:56 ` [PULL 38/46] cpu: move cc->transaction_failed " Richard Henderson
2021-02-23 21:43 ` Philippe Mathieu-Daudé
2021-02-24 8:46 ` Claudio Fontana
2021-02-05 22:56 ` [PULL 39/46] cpu: move do_unaligned_access " Richard Henderson
2021-02-05 22:56 ` Richard Henderson [this message]
2021-02-05 22:56 ` [PULL 41/46] cpu: move adjust_watchpoint_address " Richard Henderson
2021-02-05 22:56 ` [PULL 42/46] cpu: move debug_check_watchpoint " Richard Henderson
2021-02-05 22:56 ` [PULL 43/46] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass Richard Henderson
2021-02-05 22:56 ` [PULL 44/46] accel: extend AccelState and AccelClass to user-mode Richard Henderson
2021-02-05 22:56 ` [PULL 45/46] accel: replace struct CpusAccel with AccelOpsClass Richard Henderson
2021-02-05 22:56 ` [PULL 46/46] accel: introduce AccelCPUClass extending CPUClass Richard Henderson
2021-04-26 14:42 ` Philippe Mathieu-Daudé
2021-02-06 14:28 ` [PULL 00/46] tcg patch queue Peter Maydell
2021-02-06 19:14 ` Philippe Mathieu-Daudé
2021-02-06 19:38 ` Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue) Stefan Weil
2021-02-07 3:45 ` Richard Henderson
2021-02-07 10:50 ` Stefan Weil
2021-02-07 18:37 ` Richard Henderson
2021-02-07 22:00 ` Stefan Weil
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