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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Alex Bennée" <alex.bennee@linaro.org>,
	"Claudio Fontana" <cfontana@suse.de>
Subject: [PULL 41/46] cpu: move adjust_watchpoint_address to tcg_ops
Date: Fri,  5 Feb 2021 12:56:45 -1000	[thread overview]
Message-ID: <20210205225650.1330794-42-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210205225650.1330794-1-richard.henderson@linaro.org>

From: Claudio Fontana <cfontana@suse.de>

commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")

introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.

Make adjust_watchpoint_address optional and move it to tcg_ops.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-14-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/core/cpu.h | 6 +++++-
 hw/core/cpu.c         | 6 ------
 softmmu/physmem.c     | 5 ++++-
 target/arm/cpu.c      | 2 +-
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 063814eaa4..832dd26e92 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -136,6 +136,11 @@ typedef struct TcgCpuOperations {
     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
                                 MMUAccessType access_type,
                                 int mmu_idx, uintptr_t retaddr);
+    /**
+     * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
+     */
+    vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+
 } TcgCpuOperations;
 
 /**
@@ -244,7 +249,6 @@ struct CPUClass {
     const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
 
     void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
-    vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
 
     const char *deprecation_note;
     /* Keep non-pointer data at the end to minimize holes.  */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 57542b6906..3d5bf9fe02 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -383,11 +383,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
     return cpu->cpu_index;
 }
 
-static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
-{
-    return addr;
-}
-
 static Property cpu_common_props[] = {
 #ifndef CONFIG_USER_ONLY
     /* Create a memory property for softmmu CPU object,
@@ -421,7 +416,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
     k->gdb_write_register = cpu_common_gdb_write_register;
     k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
     k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
-    k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
     dc->realize = cpu_common_realizefn;
     dc->unrealize = cpu_common_unrealizefn;
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 51ed600bf9..3d9a9c39bd 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -894,7 +894,10 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
         return;
     }
 
-    addr = cc->adjust_watchpoint_address(cpu, addr, len);
+    if (cc->tcg_ops.adjust_watchpoint_address) {
+        /* this is currently used only by ARM BE32 */
+        addr = cc->tcg_ops.adjust_watchpoint_address(cpu, addr, len);
+    }
     QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
         if (watchpoint_address_matches(wp, addr, len)
             && (wp->flags & flags)) {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index aa264eec0a..2a14431065 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2284,7 +2284,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
 #if !defined(CONFIG_USER_ONLY)
     cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
     cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
-    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+    cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
     cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
 #endif /* CONFIG_TCG */
-- 
2.25.1



  parent reply	other threads:[~2021-02-05 23:29 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
2021-02-05 22:56 ` [PULL 01/46] tcg/s390: Fix compare instruction from extended-immediate facility Richard Henderson
2021-02-05 22:56 ` [PULL 02/46] exec/cpu-defs: Remove TCG backends dependency Richard Henderson
2021-02-05 22:56 ` [PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps Richard Henderson
2021-02-05 22:56 ` [PULL 04/46] configure: Fix --enable-tcg-interpreter Richard Henderson
2021-02-05 22:56 ` [PULL 05/46] tcg/tci: Make tci_tb_ptr thread-local Richard Henderson
2021-02-05 22:56 ` [PULL 06/46] tcg/tci: Implement INDEX_op_ld16s_i32 Richard Henderson
2021-02-05 22:56 ` [PULL 07/46] tcg/tci: Implement INDEX_op_ld8s_i64 Richard Henderson
2021-02-05 22:56 ` [PULL 08/46] tcg/tci: Inline tci_write_reg32s into the only caller Richard Henderson
2021-02-05 22:56 ` [PULL 09/46] tcg/tci: Inline tci_write_reg8 into its callers Richard Henderson
2021-02-05 22:56 ` [PULL 10/46] tcg/tci: Inline tci_write_reg16 into the only caller Richard Henderson
2021-02-05 22:56 ` [PULL 11/46] tcg/tci: Inline tci_write_reg32 into all callers Richard Henderson
2021-02-05 22:56 ` [PULL 12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers Richard Henderson
2021-02-05 22:56 ` [PULL 13/46] tcg/tci: Merge INDEX_op_ld8u_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 15/46] tcg/tci: Merge INDEX_op_ld16u_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 16/46] tcg/tci: Merge INDEX_op_ld16s_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 17/46] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64} Richard Henderson
2021-02-05 22:56 ` [PULL 18/46] tcg/tci: Merge INDEX_op_st8_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 19/46] tcg/tci: Merge INDEX_op_st16_{i32,i64} Richard Henderson
2021-02-05 22:56 ` [PULL 20/46] tcg/tci: Move stack bounds check to compile-time Richard Henderson
2021-02-05 22:56 ` [PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64} Richard Henderson
2021-02-05 22:56 ` [PULL 22/46] tcg/tci: Use g_assert_not_reached Richard Henderson
2021-02-05 22:56 ` [PULL 23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* Richard Henderson
2021-02-05 22:56 ` [PULL 24/46] tcg/tci: Implement 64-bit division Richard Henderson
2021-02-05 22:56 ` [PULL 25/46] tcg/tci: Remove TODO as unused Richard Henderson
2021-02-05 22:56 ` [PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 Richard Henderson
2021-02-05 22:56 ` [PULL 27/46] tcg/tci: Fix TCG_REG_R4 misusage Richard Henderson
2021-02-05 22:56 ` [PULL 28/46] tcg/tci: Remove TCG_CONST Richard Henderson
2021-02-05 22:56 ` [PULL 29/46] cpu: Introduce TCGCpuOperations struct Richard Henderson
2021-02-05 22:56 ` [PULL 30/46] target/riscv: remove CONFIG_TCG, as it is always TCG Richard Henderson
2021-02-05 22:56 ` [PULL 31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn Richard Henderson
2021-02-05 22:56 ` [PULL 32/46] cpu: Move synchronize_from_tb() to tcg_ops Richard Henderson
2021-02-05 22:56 ` [PULL 33/46] cpu: Move cpu_exec_* " Richard Henderson
2021-02-05 22:56 ` [PULL 34/46] cpu: Move tlb_fill " Richard Henderson
2021-02-05 22:56 ` [PULL 35/46] cpu: Move debug_excp_handler " Richard Henderson
2021-02-05 22:56 ` [PULL 36/46] target/arm: do not use cc->do_interrupt for KVM directly Richard Henderson
2021-02-05 22:56 ` [PULL 37/46] cpu: move cc->do_interrupt to tcg_ops Richard Henderson
2021-02-05 22:56 ` [PULL 38/46] cpu: move cc->transaction_failed " Richard Henderson
2021-02-23 21:43   ` Philippe Mathieu-Daudé
2021-02-24  8:46     ` Claudio Fontana
2021-02-05 22:56 ` [PULL 39/46] cpu: move do_unaligned_access " Richard Henderson
2021-02-05 22:56 ` [PULL 40/46] physmem: make watchpoint checking code TCG-only Richard Henderson
2021-02-05 22:56 ` Richard Henderson [this message]
2021-02-05 22:56 ` [PULL 42/46] cpu: move debug_check_watchpoint to tcg_ops Richard Henderson
2021-02-05 22:56 ` [PULL 43/46] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass Richard Henderson
2021-02-05 22:56 ` [PULL 44/46] accel: extend AccelState and AccelClass to user-mode Richard Henderson
2021-02-05 22:56 ` [PULL 45/46] accel: replace struct CpusAccel with AccelOpsClass Richard Henderson
2021-02-05 22:56 ` [PULL 46/46] accel: introduce AccelCPUClass extending CPUClass Richard Henderson
2021-04-26 14:42   ` Philippe Mathieu-Daudé
2021-02-06 14:28 ` [PULL 00/46] tcg patch queue Peter Maydell
2021-02-06 19:14   ` Philippe Mathieu-Daudé
2021-02-06 19:38 ` Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue) Stefan Weil
2021-02-07  3:45   ` Richard Henderson
2021-02-07 10:50     ` Stefan Weil
2021-02-07 18:37       ` Richard Henderson
2021-02-07 22:00         ` Stefan Weil

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