From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: sw@weilnetz.de
Subject: [PATCH v3 11/70] tcg/tci: Reduce use of tci_read_r64
Date: Sun, 7 Feb 2021 18:36:53 -0800 [thread overview]
Message-ID: <20210208023752.270606-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org>
In all cases restricted to 64-bit hosts, tcg_read_r is
identical. We retain the 64-bit symbol for the single
case of INDEX_op_qemu_st_i64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------
1 file changed, 42 insertions(+), 51 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 9c8395397a..0246e663a3 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
return regs[index];
}
-#if TCG_TARGET_REG_BITS == 64
-static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
-{
- return tci_read_reg(regs, index);
-}
-#endif
-
static void
tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
{
@@ -146,9 +139,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
{
- uint64_t value = tci_read_reg64(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
+ return tci_read_r(regs, tb_ptr);
}
#endif
@@ -407,8 +398,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break;
@@ -689,7 +680,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_mov_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i64:
@@ -713,7 +704,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st_i64:
- t0 = tci_read_r64(regs, &tb_ptr);
+ t0 = tci_read_r(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint64_t *)(t1 + t2) = t0;
@@ -723,62 +714,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_add_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
case INDEX_op_div_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
break;
case INDEX_op_divu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
break;
case INDEX_op_rem_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
break;
case INDEX_op_remu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
break;
case INDEX_op_and_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2);
break;
case INDEX_op_or_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2);
break;
case INDEX_op_xor_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2);
break;
@@ -786,41 +777,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, rol64(t1, t2 & 63));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ror64(t1, t2 & 63));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_r(regs, &tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
@@ -828,8 +819,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i64:
- t0 = tci_read_r64(regs, &tb_ptr);
- t1 = tci_read_r64(regs, &tb_ptr);
+ t0 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(t0, t1, condition)) {
@@ -899,21 +890,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap64(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i64
case INDEX_op_not_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i64
case INDEX_op_neg_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r64(regs, &tb_ptr);
+ t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, -t1);
break;
#endif
--
2.25.1
next prev parent reply other threads:[~2021-02-08 2:52 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-08 2:36 [PATCH v3 00/70] TCI fixes and cleanups Richard Henderson
2021-02-08 2:36 ` [PATCH v3 01/70] gdbstub: Fix handle_query_xfer_auxv Richard Henderson
2021-02-08 2:36 ` [PATCH v3 02/70] tcg: Split out tcg_raise_tb_overflow Richard Henderson
2021-03-05 14:48 ` Alex Bennée
2021-02-08 2:36 ` [PATCH v3 03/70] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Richard Henderson
2021-03-05 15:28 ` Alex Bennée
2021-02-08 2:36 ` [PATCH v3 04/70] tcg/tci: Merge identical cases in generation Richard Henderson
2021-03-05 16:29 ` Alex Bennée
2021-02-08 2:36 ` [PATCH v3 05/70] tcg/tci: Remove tci_read_r8 Richard Henderson
2021-03-05 16:34 ` Alex Bennée
2021-02-08 2:36 ` [PATCH v3 06/70] tcg/tci: Remove tci_read_r8s Richard Henderson
2021-02-08 2:36 ` [PATCH v3 07/70] tcg/tci: Remove tci_read_r16 Richard Henderson
2021-02-08 2:36 ` [PATCH v3 08/70] tcg/tci: Remove tci_read_r16s Richard Henderson
2021-02-08 2:36 ` [PATCH v3 09/70] tcg/tci: Remove tci_read_r32 Richard Henderson
2021-02-08 2:36 ` [PATCH v3 10/70] tcg/tci: Remove tci_read_r32s Richard Henderson
2021-02-08 2:36 ` Richard Henderson [this message]
2021-02-08 2:36 ` [PATCH v3 12/70] tcg/tci: Merge basic arithmetic operations Richard Henderson
2021-02-08 2:36 ` [PATCH v3 13/70] tcg/tci: Merge extension operations Richard Henderson
2021-02-08 2:36 ` [PATCH v3 14/70] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
2021-02-08 2:36 ` [PATCH v3 15/70] tcg/tci: Merge bswap operations Richard Henderson
2021-02-08 2:36 ` [PATCH v3 16/70] tcg/tci: Merge mov, not and neg operations Richard Henderson
2021-02-08 2:36 ` [PATCH v3 17/70] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
2021-02-08 2:37 ` [PATCH v3 18/70] tcg/tci: Split out tci_args_rrs Richard Henderson
2021-02-08 2:37 ` [PATCH v3 19/70] tcg/tci: Split out tci_args_rr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 20/70] tcg/tci: Split out tci_args_rrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 21/70] tcg/tci: Split out tci_args_rrrc Richard Henderson
2021-02-08 2:37 ` [PATCH v3 22/70] tcg/tci: Split out tci_args_l Richard Henderson
2021-02-08 2:37 ` [PATCH v3 23/70] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
2021-02-08 2:37 ` [PATCH v3 24/70] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
2021-02-08 2:37 ` [PATCH v3 25/70] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
2021-02-08 2:37 ` [PATCH v3 26/70] tcg/tci: Reuse tci_args_l for calls Richard Henderson
2021-02-08 2:37 ` [PATCH v3 27/70] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
2021-02-08 2:37 ` [PATCH v3 28/70] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
2021-02-08 2:37 ` [PATCH v3 29/70] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 30/70] tcg/tci: Split out tci_args_rrrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 31/70] tcg/tci: Clean up deposit operations Richard Henderson
2021-02-08 2:37 ` [PATCH v3 32/70] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
2021-02-08 2:37 ` [PATCH v3 33/70] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-08 2:37 ` [PATCH v3 34/70] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
2021-02-08 2:37 ` [PATCH v3 35/70] tcg/tci: Remove tci_disas Richard Henderson
2021-02-08 2:37 ` [PATCH v3 36/70] tcg/tci: Implement the disassembler properly Richard Henderson
2021-02-08 2:37 ` [PATCH v3 37/70] tcg: Build ffi data structures for helpers Richard Henderson
2021-02-08 2:37 ` [PATCH v3 38/70] tcg/tci: Use ffi for calls Richard Henderson
2021-02-08 2:37 ` [PATCH v3 39/70] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-02-08 2:37 ` [PATCH v3 40/70] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-02-08 2:37 ` [PATCH v3 41/70] tcg/tci: Push opcode emit into each case Richard Henderson
2021-02-08 2:37 ` [PATCH v3 42/70] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
2021-02-08 2:37 ` [PATCH v3 43/70] tcg/tci: Split out tcg_out_op_l Richard Henderson
2021-02-08 2:37 ` [PATCH v3 44/70] tcg/tci: Split out tcg_out_op_p Richard Henderson
2021-02-08 2:37 ` [PATCH v3 45/70] tcg/tci: Split out tcg_out_op_rr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 46/70] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 47/70] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
2021-02-08 2:37 ` [PATCH v3 48/70] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
2021-02-08 2:37 ` [PATCH v3 49/70] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
2021-02-08 2:37 ` [PATCH v3 50/70] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
2021-02-08 2:37 ` [PATCH v3 51/70] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 52/70] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 53/70] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
2021-02-08 2:37 ` [PATCH v3 54/70] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-08 2:37 ` [PATCH v3 55/70] tcg/tci: Split out tcg_out_op_v Richard Henderson
2021-02-08 2:37 ` [PATCH v3 56/70] tcg/tci: Split out tcg_out_op_np Richard Henderson
2021-02-08 2:37 ` [PATCH v3 57/70] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
2021-02-08 2:37 ` [PATCH v3 58/70] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-02-08 2:37 ` [PATCH v3 59/70] tcg/tci: Emit setcond before brcond Richard Henderson
2021-02-08 2:37 ` [PATCH v3 60/70] tcg/tci: Remove tci_write_reg Richard Henderson
2021-02-08 2:37 ` [PATCH v3 61/70] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-02-08 2:37 ` [PATCH v3 62/70] tcg/tci: Implement goto_ptr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 63/70] tcg/tci: Implement movcond Richard Henderson
2021-02-08 2:37 ` [PATCH v3 64/70] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-02-08 2:37 ` [PATCH v3 65/70] tcg/tci: Implement extract, sextract Richard Henderson
2021-02-08 2:37 ` [PATCH v3 66/70] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-02-08 2:37 ` [PATCH v3 67/70] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-02-08 2:37 ` [PATCH v3 68/70] tcg/tci: Implement add2, sub2 Richard Henderson
2021-02-08 2:37 ` [PATCH v3 69/70] tests/tcg: Increase timeout for TCI Richard Henderson
2021-02-08 2:37 ` [PATCH v3 70/70] gitlab: Enable cross-i386 builds of TCI Richard Henderson
2021-02-17 17:25 ` Philippe Mathieu-Daudé
2021-02-08 3:45 ` [PATCH v3 00/70] TCI fixes and cleanups no-reply
2021-03-05 16:37 ` Alex Bennée
2021-03-05 16:55 ` Philippe Mathieu-Daudé
2021-03-05 16:55 ` Alex Bennée
2021-03-05 16:59 ` Alex Bennée
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