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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id j17sm16158689pfh.183.2021.02.07.18.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:38:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 27/70] tcg/tci: Reuse tci_args_l for exit_tb Date: Sun, 7 Feb 2021 18:37:09 -0800 Message-Id: <20210208023752.270606-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org> References: <20210208023752.270606-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Do not emit a uint64_t, but a tcg_target_ulong, aka uintptr_t. This reduces the size of the constant on 32-bit hosts. The assert for label != NULL has to be removed because that is a valid value for exit_tb. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++++--------- tcg/tci/tcg-target.c.inc | 2 +- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 92b13829c3..57b6defe09 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -160,9 +160,7 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) { - tcg_target_ulong label = tci_read_i(tb_ptr); - tci_assert(label != 0); - return label; + return tci_read_i(tb_ptr); } /* @@ -417,7 +415,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); - uintptr_t ret = 0; regs[TCG_AREG0] = (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] = sp_value; @@ -832,9 +829,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* QEMU specific operations. */ case INDEX_op_exit_tb: - ret = *(uint64_t *)tb_ptr; - goto exit; - break; + tci_args_l(&tb_ptr, &ptr); + return (uintptr_t)ptr; + case INDEX_op_goto_tb: /* Jump address is aligned */ tb_ptr = QEMU_ALIGN_PTR_UP(tb_ptr, 4); @@ -992,6 +989,4 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, } tci_assert(tb_ptr == old_code_ptr + op_size); } -exit: - return ret; } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c79f9c32d8..ff8040510f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -401,7 +401,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, switch (opc) { case INDEX_op_exit_tb: - tcg_out64(s, args[0]); + tcg_out_i(s, args[0]); break; case INDEX_op_goto_tb: -- 2.25.1