From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: sw@weilnetz.de
Subject: [PATCH v3 33/70] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm}
Date: Sun, 7 Feb 2021 18:37:15 -0800 [thread overview]
Message-ID: <20210208023752.270606-34-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210208023752.270606-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 147 ++++++++++++++++++++++++++++++------------------------
1 file changed, 81 insertions(+), 66 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index ddc138359b..a1846825ea 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -66,22 +66,18 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
regs[index] = value;
}
-#if TCG_TARGET_REG_BITS == 32
static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
uint32_t low_index, uint64_t value)
{
tci_write_reg(regs, low_index, value);
tci_write_reg(regs, high_index, value >> 32);
}
-#endif
-#if TCG_TARGET_REG_BITS == 32
/* Create a 64 bit value from two 32 bit values. */
static uint64_t tci_uint64(uint32_t high, uint32_t low)
{
return ((uint64_t)high << 32) + low;
}
-#endif
/* Read constant byte from bytecode. */
static uint8_t tci_read_b(const uint8_t **tb_ptr)
@@ -121,43 +117,6 @@ static int32_t tci_read_s32(const uint8_t **tb_ptr)
return value;
}
-/* Read indexed register (native size) from bytecode. */
-static tcg_target_ulong
-tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
-{
- tcg_target_ulong value = tci_read_reg(regs, **tb_ptr);
- *tb_ptr += 1;
- return value;
-}
-
-#if TCG_TARGET_REG_BITS == 32
-/* Read two indexed registers (2 * 32 bit) from bytecode. */
-static uint64_t tci_read_r64(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- uint32_t low = tci_read_rval(regs, tb_ptr);
- return tci_uint64(tci_read_rval(regs, tb_ptr), low);
-}
-#elif TCG_TARGET_REG_BITS == 64
-/* Read indexed register (64 bit) from bytecode. */
-static uint64_t tci_read_r64(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- return tci_read_rval(regs, tb_ptr);
-}
-#endif
-
-/* Read indexed register(s) with target address from bytecode. */
-static target_ulong
-tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
-{
- target_ulong taddr = tci_read_rval(regs, tb_ptr);
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
- taddr += (uint64_t)tci_read_rval(regs, tb_ptr) << 32;
-#endif
- return taddr;
-}
-
static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
{
return tci_read_i(tb_ptr);
@@ -171,6 +130,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
* b = immediate (bit position)
* i = immediate (uint32_t)
* I = immediate (tcg_target_ulong)
+ * m = immediate (TCGMemOpIdx)
* r = register
* s = signed ldst offset
*/
@@ -203,6 +163,14 @@ static void tci_args_rI(const uint8_t **tb_ptr,
}
#endif
+static void tci_args_rrm(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGMemOpIdx *m2)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *m2 = tci_read_i32(tb_ptr);
+}
+
static void tci_args_rrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2)
{
@@ -237,6 +205,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
*c3 = tci_read_b(tb_ptr);
}
+static void tci_args_rrrm(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *m3 = tci_read_i32(tb_ptr);
+}
+
static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, uint8_t *i3, uint8_t *i4)
{
@@ -247,6 +224,16 @@ static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
*i4 = tci_read_b(tb_ptr);
}
+static void tci_args_rrrrm(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, TCGReg *r3, TCGMemOpIdx *m4)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *r3 = tci_read_r(tb_ptr);
+ *m4 = tci_read_i32(tb_ptr);
+}
+
#if TCG_TARGET_REG_BITS == 32
static void tci_args_rrrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
@@ -457,8 +444,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint8_t op_size = tb_ptr[1];
const uint8_t *old_code_ptr = tb_ptr;
#endif
- TCGReg r0, r1, r2;
- tcg_target_ulong t0;
+ TCGReg r0, r1, r2, r3;
tcg_target_ulong t1;
TCGCond condition;
target_ulong taddr;
@@ -466,7 +452,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
- TCGReg r3, r4, r5;
+ TCGReg r4, r5;
uint64_t T1, T2;
#endif
TCGMemOpIdx oi;
@@ -853,9 +839,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue;
case INDEX_op_qemu_ld_i32:
- t0 = *tb_ptr++;
- taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i32(&tb_ptr);
+ if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ taddr = regs[r1];
+ } else {
+ tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ taddr = tci_uint64(regs[r2], regs[r1]);
+ }
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp32 = qemu_ld_ub;
@@ -884,15 +874,20 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
default:
g_assert_not_reached();
}
- tci_write_reg(regs, t0, tmp32);
+ regs[r0] = tmp32;
break;
+
case INDEX_op_qemu_ld_i64:
- t0 = *tb_ptr++;
- if (TCG_TARGET_REG_BITS == 32) {
- t1 = *tb_ptr++;
+ if (TCG_TARGET_REG_BITS == 64) {
+ tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ taddr = regs[r1];
+ } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ taddr = regs[r2];
+ } else {
+ tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
+ taddr = tci_uint64(regs[r3], regs[r2]);
}
- taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i32(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp64 = qemu_ld_ub;
@@ -933,39 +928,58 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
default:
g_assert_not_reached();
}
- tci_write_reg(regs, t0, tmp64);
if (TCG_TARGET_REG_BITS == 32) {
- tci_write_reg(regs, t1, tmp64 >> 32);
+ tci_write_reg64(regs, r1, r0, tmp64);
+ } else {
+ regs[r0] = tmp64;
}
break;
+
case INDEX_op_qemu_st_i32:
- t0 = tci_read_rval(regs, &tb_ptr);
- taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i32(&tb_ptr);
+ if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ taddr = regs[r1];
+ } else {
+ tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ taddr = tci_uint64(regs[r2], regs[r1]);
+ }
+ tmp32 = regs[r0];
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
- qemu_st_b(t0);
+ qemu_st_b(tmp32);
break;
case MO_LEUW:
- qemu_st_lew(t0);
+ qemu_st_lew(tmp32);
break;
case MO_LEUL:
- qemu_st_lel(t0);
+ qemu_st_lel(tmp32);
break;
case MO_BEUW:
- qemu_st_bew(t0);
+ qemu_st_bew(tmp32);
break;
case MO_BEUL:
- qemu_st_bel(t0);
+ qemu_st_bel(tmp32);
break;
default:
g_assert_not_reached();
}
break;
+
case INDEX_op_qemu_st_i64:
- tmp64 = tci_read_r64(regs, &tb_ptr);
- taddr = tci_read_ulong(regs, &tb_ptr);
- oi = tci_read_i32(&tb_ptr);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tci_args_rrm(&tb_ptr, &r0, &r1, &oi);
+ taddr = regs[r1];
+ tmp64 = regs[r0];
+ } else {
+ if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
+ tci_args_rrrm(&tb_ptr, &r0, &r1, &r2, &oi);
+ taddr = regs[r2];
+ } else {
+ tci_args_rrrrm(&tb_ptr, &r0, &r1, &r2, &r3, &oi);
+ taddr = tci_uint64(regs[r3], regs[r2]);
+ }
+ tmp64 = tci_uint64(regs[r1], regs[r0]);
+ }
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
qemu_st_b(tmp64);
@@ -992,6 +1006,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
g_assert_not_reached();
}
break;
+
case INDEX_op_mb:
/* Ensure ordering for all kinds */
smp_mb();
--
2.25.1
next prev parent reply other threads:[~2021-02-08 3:07 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-08 2:36 [PATCH v3 00/70] TCI fixes and cleanups Richard Henderson
2021-02-08 2:36 ` [PATCH v3 01/70] gdbstub: Fix handle_query_xfer_auxv Richard Henderson
2021-02-08 2:36 ` [PATCH v3 02/70] tcg: Split out tcg_raise_tb_overflow Richard Henderson
2021-03-05 14:48 ` Alex Bennée
2021-02-08 2:36 ` [PATCH v3 03/70] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Richard Henderson
2021-03-05 15:28 ` Alex Bennée
2021-02-08 2:36 ` [PATCH v3 04/70] tcg/tci: Merge identical cases in generation Richard Henderson
2021-03-05 16:29 ` Alex Bennée
2021-02-08 2:36 ` [PATCH v3 05/70] tcg/tci: Remove tci_read_r8 Richard Henderson
2021-03-05 16:34 ` Alex Bennée
2021-02-08 2:36 ` [PATCH v3 06/70] tcg/tci: Remove tci_read_r8s Richard Henderson
2021-02-08 2:36 ` [PATCH v3 07/70] tcg/tci: Remove tci_read_r16 Richard Henderson
2021-02-08 2:36 ` [PATCH v3 08/70] tcg/tci: Remove tci_read_r16s Richard Henderson
2021-02-08 2:36 ` [PATCH v3 09/70] tcg/tci: Remove tci_read_r32 Richard Henderson
2021-02-08 2:36 ` [PATCH v3 10/70] tcg/tci: Remove tci_read_r32s Richard Henderson
2021-02-08 2:36 ` [PATCH v3 11/70] tcg/tci: Reduce use of tci_read_r64 Richard Henderson
2021-02-08 2:36 ` [PATCH v3 12/70] tcg/tci: Merge basic arithmetic operations Richard Henderson
2021-02-08 2:36 ` [PATCH v3 13/70] tcg/tci: Merge extension operations Richard Henderson
2021-02-08 2:36 ` [PATCH v3 14/70] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
2021-02-08 2:36 ` [PATCH v3 15/70] tcg/tci: Merge bswap operations Richard Henderson
2021-02-08 2:36 ` [PATCH v3 16/70] tcg/tci: Merge mov, not and neg operations Richard Henderson
2021-02-08 2:36 ` [PATCH v3 17/70] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
2021-02-08 2:37 ` [PATCH v3 18/70] tcg/tci: Split out tci_args_rrs Richard Henderson
2021-02-08 2:37 ` [PATCH v3 19/70] tcg/tci: Split out tci_args_rr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 20/70] tcg/tci: Split out tci_args_rrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 21/70] tcg/tci: Split out tci_args_rrrc Richard Henderson
2021-02-08 2:37 ` [PATCH v3 22/70] tcg/tci: Split out tci_args_l Richard Henderson
2021-02-08 2:37 ` [PATCH v3 23/70] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
2021-02-08 2:37 ` [PATCH v3 24/70] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
2021-02-08 2:37 ` [PATCH v3 25/70] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
2021-02-08 2:37 ` [PATCH v3 26/70] tcg/tci: Reuse tci_args_l for calls Richard Henderson
2021-02-08 2:37 ` [PATCH v3 27/70] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
2021-02-08 2:37 ` [PATCH v3 28/70] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
2021-02-08 2:37 ` [PATCH v3 29/70] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 30/70] tcg/tci: Split out tci_args_rrrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 31/70] tcg/tci: Clean up deposit operations Richard Henderson
2021-02-08 2:37 ` [PATCH v3 32/70] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
2021-02-08 2:37 ` Richard Henderson [this message]
2021-02-08 2:37 ` [PATCH v3 34/70] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
2021-02-08 2:37 ` [PATCH v3 35/70] tcg/tci: Remove tci_disas Richard Henderson
2021-02-08 2:37 ` [PATCH v3 36/70] tcg/tci: Implement the disassembler properly Richard Henderson
2021-02-08 2:37 ` [PATCH v3 37/70] tcg: Build ffi data structures for helpers Richard Henderson
2021-02-08 2:37 ` [PATCH v3 38/70] tcg/tci: Use ffi for calls Richard Henderson
2021-02-08 2:37 ` [PATCH v3 39/70] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-02-08 2:37 ` [PATCH v3 40/70] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-02-08 2:37 ` [PATCH v3 41/70] tcg/tci: Push opcode emit into each case Richard Henderson
2021-02-08 2:37 ` [PATCH v3 42/70] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
2021-02-08 2:37 ` [PATCH v3 43/70] tcg/tci: Split out tcg_out_op_l Richard Henderson
2021-02-08 2:37 ` [PATCH v3 44/70] tcg/tci: Split out tcg_out_op_p Richard Henderson
2021-02-08 2:37 ` [PATCH v3 45/70] tcg/tci: Split out tcg_out_op_rr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 46/70] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 47/70] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
2021-02-08 2:37 ` [PATCH v3 48/70] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
2021-02-08 2:37 ` [PATCH v3 49/70] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
2021-02-08 2:37 ` [PATCH v3 50/70] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
2021-02-08 2:37 ` [PATCH v3 51/70] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 52/70] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 53/70] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
2021-02-08 2:37 ` [PATCH v3 54/70] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-08 2:37 ` [PATCH v3 55/70] tcg/tci: Split out tcg_out_op_v Richard Henderson
2021-02-08 2:37 ` [PATCH v3 56/70] tcg/tci: Split out tcg_out_op_np Richard Henderson
2021-02-08 2:37 ` [PATCH v3 57/70] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
2021-02-08 2:37 ` [PATCH v3 58/70] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-02-08 2:37 ` [PATCH v3 59/70] tcg/tci: Emit setcond before brcond Richard Henderson
2021-02-08 2:37 ` [PATCH v3 60/70] tcg/tci: Remove tci_write_reg Richard Henderson
2021-02-08 2:37 ` [PATCH v3 61/70] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-02-08 2:37 ` [PATCH v3 62/70] tcg/tci: Implement goto_ptr Richard Henderson
2021-02-08 2:37 ` [PATCH v3 63/70] tcg/tci: Implement movcond Richard Henderson
2021-02-08 2:37 ` [PATCH v3 64/70] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-02-08 2:37 ` [PATCH v3 65/70] tcg/tci: Implement extract, sextract Richard Henderson
2021-02-08 2:37 ` [PATCH v3 66/70] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-02-08 2:37 ` [PATCH v3 67/70] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-02-08 2:37 ` [PATCH v3 68/70] tcg/tci: Implement add2, sub2 Richard Henderson
2021-02-08 2:37 ` [PATCH v3 69/70] tests/tcg: Increase timeout for TCI Richard Henderson
2021-02-08 2:37 ` [PATCH v3 70/70] gitlab: Enable cross-i386 builds of TCI Richard Henderson
2021-02-17 17:25 ` Philippe Mathieu-Daudé
2021-02-08 3:45 ` [PATCH v3 00/70] TCI fixes and cleanups no-reply
2021-03-05 16:37 ` Alex Bennée
2021-03-05 16:55 ` Alex Bennée
2021-03-05 16:59 ` Alex Bennée
2021-03-05 16:55 ` Philippe Mathieu-Daudé
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