From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v2 09/16] tcg/s390x: Implement andc, orc, abs, neg, not vector operations
Date: Sun, 7 Feb 2021 18:50:54 -0800 [thread overview]
Message-ID: <20210208025101.271726-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org>
These logical and arithmetic operations are optional but trivial.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.h | 10 +++++-----
tcg/s390x/tcg-target.c.inc | 34 +++++++++++++++++++++++++++++++++-
3 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index ce9432cfe3..cb953896d5 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -17,6 +17,7 @@ C_O0_I2(v, r)
C_O1_I1(r, L)
C_O1_I1(r, r)
C_O1_I1(v, r)
+C_O1_I1(v, v)
C_O1_I1(v, vr)
C_O1_I2(r, 0, ri)
C_O1_I2(r, 0, rI)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index e8659bf576..dd11972ed2 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -140,11 +140,11 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR)
#define TCG_TARGET_HAS_v256 0
-#define TCG_TARGET_HAS_andc_vec 0
-#define TCG_TARGET_HAS_orc_vec 0
-#define TCG_TARGET_HAS_not_vec 0
-#define TCG_TARGET_HAS_neg_vec 0
-#define TCG_TARGET_HAS_abs_vec 0
+#define TCG_TARGET_HAS_andc_vec 1
+#define TCG_TARGET_HAS_orc_vec 1
+#define TCG_TARGET_HAS_not_vec 1
+#define TCG_TARGET_HAS_neg_vec 1
+#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 08315c7b05..23c25ff619 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -270,13 +270,18 @@ typedef enum S390Opcode {
VRIb_VGM = 0xe746,
VRIc_VREP = 0xe74d,
+ VRRa_VLC = 0xe7de,
+ VRRa_VLP = 0xe7df,
VRRa_VLR = 0xe756,
VRRc_VA = 0xe7f3,
VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
VRRc_VCH = 0xe7fb, /* " */
VRRc_VCHL = 0xe7f9, /* " */
VRRc_VN = 0xe768,
+ VRRc_VNC = 0xe769,
+ VRRc_VNO = 0xe76b,
VRRc_VO = 0xe76a,
+ VRRc_VOC = 0xe76f,
VRRc_VS = 0xe7f7,
VRRc_VX = 0xe76d,
VRRf_VLVGP = 0xe762,
@@ -2634,6 +2639,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
break;
+ case INDEX_op_abs_vec:
+ tcg_out_insn(s, VRRa, VLP, a0, a1, vece);
+ break;
+ case INDEX_op_neg_vec:
+ tcg_out_insn(s, VRRa, VLC, a0, a1, vece);
+ break;
+ case INDEX_op_not_vec:
+ tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0);
+ break;
+
case INDEX_op_add_vec:
tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece);
break;
@@ -2643,9 +2658,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_and_vec:
tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0);
break;
+ case INDEX_op_andc_vec:
+ tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0);
+ break;
case INDEX_op_or_vec:
tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0);
break;
+ case INDEX_op_orc_vec:
+ tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0);
+ break;
case INDEX_op_xor_vec:
tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
break;
@@ -2676,10 +2697,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
{
switch (opc) {
+ case INDEX_op_abs_vec:
case INDEX_op_add_vec:
- case INDEX_op_sub_vec:
case INDEX_op_and_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_not_vec:
case INDEX_op_or_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_sub_vec:
case INDEX_op_xor_vec:
return 1;
case INDEX_op_cmp_vec:
@@ -2908,10 +2934,16 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return C_O1_I1(v, r);
case INDEX_op_dup_vec:
return C_O1_I1(v, vr);
+ case INDEX_op_abs_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_not_vec:
+ return C_O1_I1(v, v);
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
case INDEX_op_and_vec:
+ case INDEX_op_andc_vec:
case INDEX_op_or_vec:
+ case INDEX_op_orc_vec:
case INDEX_op_xor_vec:
case INDEX_op_cmp_vec:
return C_O1_I2(v, v, v);
--
2.25.1
next prev parent reply other threads:[~2021-02-08 4:12 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-08 2:50 [PATCH v2 00/16] tcg/s390x: host vector support Richard Henderson
2021-02-08 2:50 ` [PATCH v2 01/16] tcg/s390x: Rename from tcg/s390 Richard Henderson
2021-02-08 2:50 ` [PATCH v2 02/16] tcg/s390x: Change FACILITY representation Richard Henderson
2021-02-08 2:50 ` [PATCH v2 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Richard Henderson
2021-02-08 2:50 ` [PATCH v2 04/16] tcg/s390x: Add host vector framework Richard Henderson
2021-02-08 2:50 ` [PATCH v2 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types Richard Henderson
2021-02-08 2:50 ` [PATCH v2 06/16] tcg/s390x: Implement tcg_out_mov " Richard Henderson
2021-02-08 2:50 ` [PATCH v2 07/16] tcg/s390x: Implement tcg_out_dup*_vec Richard Henderson
2021-02-08 2:50 ` [PATCH v2 08/16] tcg/s390x: Implement minimal vector operations Richard Henderson
2021-02-08 2:50 ` Richard Henderson [this message]
2021-02-08 2:50 ` [PATCH v2 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2021-02-08 2:50 ` [PATCH v2 11/16] tcg/s390x: Implement vector shift operations Richard Henderson
2021-02-08 2:50 ` [PATCH v2 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2021-02-08 2:50 ` [PATCH v2 13/16] tcg: Expand usadd/ussub with umin/umax Richard Henderson
2021-02-08 2:50 ` [PATCH v2 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2021-02-08 2:51 ` [PATCH v2 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
2021-02-08 2:51 ` [PATCH v2 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec Richard Henderson
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