From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v2 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec
Date: Sun, 7 Feb 2021 18:51:01 -0800 [thread overview]
Message-ID: <20210208025101.271726-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org>
This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.c.inc | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 3c86b233b0..1888c7a5b4 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2834,6 +2834,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_xor_vec:
return 1;
case INDEX_op_cmp_vec:
+ case INDEX_op_cmpsel_vec:
case INDEX_op_rotrv_vec:
return -1;
case INDEX_op_mul_vec:
@@ -2896,6 +2897,21 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
}
}
+static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec c1, TCGv_vec c2,
+ TCGv_vec v3, TCGv_vec v4, TCGCond cond)
+{
+ TCGv_vec t = tcg_temp_new_vec(type);
+
+ if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) {
+ /* Invert the sense of the compare by swapping arguments. */
+ tcg_gen_bitsel_vec(vece, v0, t, v4, v3);
+ } else {
+ tcg_gen_bitsel_vec(vece, v0, t, v3, v4);
+ }
+ tcg_temp_free_vec(t);
+}
+
static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc)
{
@@ -2937,7 +2953,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
va_list va;
- TCGv_vec v0, v1, v2, t0;
+ TCGv_vec v0, v1, v2, v3, v4, t0;
va_start(va, a0);
v0 = temp_tcgv_vec(arg_temp(a0));
@@ -2949,6 +2965,12 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
break;
+ case INDEX_op_cmpsel_vec:
+ v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg));
+ break;
+
case INDEX_op_rotrv_vec:
t0 = tcg_temp_new_vec(type);
tcg_gen_neg_vec(vece, t0, v2);
--
2.25.1
prev parent reply other threads:[~2021-02-08 3:48 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-08 2:50 [PATCH v2 00/16] tcg/s390x: host vector support Richard Henderson
2021-02-08 2:50 ` [PATCH v2 01/16] tcg/s390x: Rename from tcg/s390 Richard Henderson
2021-02-08 2:50 ` [PATCH v2 02/16] tcg/s390x: Change FACILITY representation Richard Henderson
2021-02-08 2:50 ` [PATCH v2 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Richard Henderson
2021-02-08 2:50 ` [PATCH v2 04/16] tcg/s390x: Add host vector framework Richard Henderson
2021-02-08 2:50 ` [PATCH v2 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types Richard Henderson
2021-02-08 2:50 ` [PATCH v2 06/16] tcg/s390x: Implement tcg_out_mov " Richard Henderson
2021-02-08 2:50 ` [PATCH v2 07/16] tcg/s390x: Implement tcg_out_dup*_vec Richard Henderson
2021-02-08 2:50 ` [PATCH v2 08/16] tcg/s390x: Implement minimal vector operations Richard Henderson
2021-02-08 2:50 ` [PATCH v2 09/16] tcg/s390x: Implement andc, orc, abs, neg, not " Richard Henderson
2021-02-08 2:50 ` [PATCH v2 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2021-02-08 2:50 ` [PATCH v2 11/16] tcg/s390x: Implement vector shift operations Richard Henderson
2021-02-08 2:50 ` [PATCH v2 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2021-02-08 2:50 ` [PATCH v2 13/16] tcg: Expand usadd/ussub with umin/umax Richard Henderson
2021-02-08 2:50 ` [PATCH v2 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2021-02-08 2:51 ` [PATCH v2 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
2021-02-08 2:51 ` Richard Henderson [this message]
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