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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Chris Browy <cbrowy@avery-design.com>, <david@redhat.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
	mst@redhat.com, qemu-devel@nongnu.org, vishal.l.verma@intel.com,
	jgroves@micron.com, armbru@redhat.com, linux-cxl@vger.kernel.org,
	f4bug@amsat.org, imammedo@redhat.com, dan.j.williams@intel.com,
	ira.weiny@intel.com
Subject: Re: [RFC PATCH v1 01/01] PCIe DOE for PCIe and CXL 2.0
Date: Mon, 8 Feb 2021 10:55:51 +0000	[thread overview]
Message-ID: <20210208105551.00005c12@Huawei.com> (raw)
In-Reply-To: <593ADBD3-9A16-4875-AF5B-57E346A3460A@avery-design.com>

...

> 
> >   
> >>   
> >>>> 
> >>>> Just like you we feel what's most important is to have DOE supported so that
> >>>> UEFI and Linux kernel and drivers can progress.  We're also contributing to
> >>>> writing compliance tests for the CXL Compliance Software Development WG.    
> >>> 
> >>> Great.    
> >> 
> >> Is anyone doing the kernel enabling for it?  
> > 
> > Planning to look at this but plenty of other things on my todo list if someone
> > else gets to it first.
> > 
> > Generic DOE support should be straight forward (the infrastructure).
> > Parsing CDAT also straight forward.
> > Doing something with the results is hard unless we just provide an interface for
> > userspace to query them for a given device - or dump the table
> > (I think we do want to be able to that). 
> > 
> > What I'm really not sure on is how to handle NUMA domains that are created late
> > in the kernel boot sequence.  The  ACPI flow is set up with the assumption
> > that we can get them from SRAT very early in boot. Need to figure out how to
> > work around that. (e.g. preallocate a bunch of spare nodes for example though that's
> > ugly).  Note IIRC the kernel doesn't do runtime update of any of the ACPI
> > performance parameters yet (_SLI, _HMA) so there probably isn't any infrastructure
> > that we can reuse.
> > 
> > There is also the firmware based enumeration and description option (OS not necessarily
> > aware of CXL) in which this is all up to EDK2 and the kernel gets it all presented
> > as standard tables.  
> 
> Do we know who’s on this as part of the EDK2 development?  It would be great if they could
> address the SRAT/HMAT generation from reading CDAT.  EDK2 does address CXL 1.1 now.

No idea who, if anyone, is looking at this currently.  Perhaps ask on the EDK2 list?

Jonathan

> 
> > 
> > As you can perhaps tell from my half done reviews, this week disappeared in
> > other things so bit of catch up for me to do next week.
> > 
> > Thanks,
> > 
> > Joanthan
> > 
...


  reply	other threads:[~2021-02-08 17:45 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-04  4:53 [RFC PATCH v1 01/01] PCIe DOE for PCIe and CXL 2.0 Chris Browy
2021-02-05 16:09 ` Jonathan Cameron
2021-02-05 17:19   ` Ben Widawsky
2021-02-05 18:49     ` Jonathan Cameron
2021-02-05 19:35       ` Chris Browy
2021-02-08 10:55         ` Jonathan Cameron [this message]
2021-02-08 17:51           ` Ben Widawsky
  -- strict thread matches above, loose matches on Subject: below --
2021-02-02 17:46 [RFC PATCH v1 00/01] " Chris Browy
2021-02-02 20:43 ` [RFC PATCH v1 01/01] " Chris Browy
2021-02-03 17:23   ` Jonathan Cameron

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