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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id j20sm287043lfu.94.2021.02.10.03.39.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 03:39:51 -0800 (PST) Date: Wed, 10 Feb 2021 12:39:51 +0100 From: "Edgar E. Iglesias" To: Bin Meng Subject: Re: [PATCH v3 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues Message-ID: <20210210113951.GM477672@toto> References: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> <1612951813-50542-5-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1612951813-50542-5-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Xuzhou Cheng , Bin Meng , qemu-devel@nongnu.org, Francisco Iglesias , qemu-arm@nongnu.org, Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Feb 10, 2021 at 06:10:12PM +0800, Bin Meng wrote: > From: Xuzhou Cheng > > There are some coding convention warnings in xilinx_spips.c, > as reported by: > > $ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c > > Let's clean them up. > > Signed-off-by: Xuzhou Cheng > Signed-off-by: Bin Meng > Reviewed-by: Philippe Mathieu-Daudé > Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > > (no changes since v1) > > hw/ssi/xilinx_spips.c | 23 ++++++++++++++--------- > 1 file changed, 14 insertions(+), 9 deletions(-) > > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > index a897034..8a0cc22 100644 > --- a/hw/ssi/xilinx_spips.c > +++ b/hw/ssi/xilinx_spips.c > @@ -176,7 +176,8 @@ > FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) > #define R_GQSPI_GFIFO_THRESH (0x150 / 4) > #define R_GQSPI_DATA_STS (0x15c / 4) > -/* We use the snapshot register to hold the core state for the currently > +/* > + * We use the snapshot register to hold the core state for the currently > * or most recently executed command. So the generic fifo format is defined > * for the snapshot register > */ > @@ -424,7 +425,8 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) > xlnx_zynqmp_qspips_update_ixr(s); > } > > -/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) > +/* > + * N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) > * column wise (from element 0 to N-1). num is the length of x, and dir > * reverses the direction of the transform. Best illustrated by example: > * Each digit in the below array is a single bit (num == 3): > @@ -637,8 +639,10 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) > tx_rx[i] = tx; > } > } else { > - /* Extract a dummy byte and generate dummy cycles according to the > - * link state */ > + /* > + * Extract a dummy byte and generate dummy cycles according to the > + * link state > + */ > tx = fifo8_pop(&s->tx_fifo); > dummy_cycles = 8 / s->link_state; > } > @@ -721,8 +725,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) > } > break; > case (SNOOP_ADDR): > - /* Address has been transmitted, transmit dummy cycles now if > - * needed */ > + /* > + * Address has been transmitted, transmit dummy cycles now if needed > + */ > if (s->cmd_dummies < 0) { > s->snoop_state = SNOOP_NONE; > } else { > @@ -876,7 +881,7 @@ static void xlnx_zynqmp_qspips_notify(void *opaque) > } > > static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, > - unsigned size) > + unsigned size) > { > XilinxSPIPS *s = opaque; > uint32_t mask = ~0; > @@ -970,7 +975,7 @@ static uint64_t xlnx_zynqmp_qspips_read(void *opaque, > } > > static void xilinx_spips_write(void *opaque, hwaddr addr, > - uint64_t value, unsigned size) > + uint64_t value, unsigned size) > { > int mask = ~0; > XilinxSPIPS *s = opaque; > @@ -1072,7 +1077,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, > } > > static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, > - uint64_t value, unsigned size) > + uint64_t value, unsigned size) > { > XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); > uint32_t reg = addr / 4; > -- > 2.7.4 >