[PULL v2 00/11] target-arm queue

[PULL v2 00/11] target-arm queue

[Peter Maydell]

Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
ethernet device failed 'make check' on big-endian hosts.

-- PMM

The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:

  Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1

for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:

  target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)

----------------------------------------------------------------
target-arm queue:
 * Correctly initialize MDCR_EL2.HPMN
 * versal: Use nr_apu_cpus in favor of hard coding 2
 * accel/tcg: Add URL of clang bug to comment about our workaround
 * Add support for FEAT_DIT, Data Independent Timing
 * Remove GPIO from unimplemented NPCM7XX
 * Fix SCR RES1 handling
 * Don't migrate CPUARMState.features

----------------------------------------------------------------
Aaron Lindsay (1):
      target/arm: Don't migrate CPUARMState.features

Daniel Müller (1):
      target/arm: Correctly initialize MDCR_EL2.HPMN

Edgar E. Iglesias (1):
      hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2

Hao Wu (1):
      hw/arm: Remove GPIO from unimplemented NPCM7XX

Mike Nawrocki (1):
      target/arm: Fix SCR RES1 handling

Peter Maydell (2):
      arm: Update infocenter.arm.com URLs
      accel/tcg: Add URL of clang bug to comment about our workaround

Rebecca Cran (4):
      target/arm: Add support for FEAT_DIT, Data Independent Timing
      target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
      target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
      target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU

 include/hw/dma/pl080.h                 |  7 ++--
 include/hw/misc/arm_integrator_debug.h |  2 +-
 include/hw/ssi/pl022.h                 |  5 ++-
 target/arm/cpu.h                       | 17 ++++++++
 target/arm/internals.h                 |  6 +++
 accel/tcg/cpu-exec.c                   | 25 +++++++++---
 hw/arm/aspeed_ast2600.c                |  2 +-
 hw/arm/musca.c                         |  4 +-
 hw/arm/npcm7xx.c                       |  8 ----
 hw/arm/xlnx-versal.c                   |  4 +-
 hw/misc/arm_integrator_debug.c         |  2 +-
 hw/timer/arm_timer.c                   |  7 ++--
 target/arm/cpu.c                       |  4 ++
 target/arm/cpu64.c                     |  5 +++
 target/arm/helper-a64.c                | 27 +++++++++++--
 target/arm/helper.c                    | 71 +++++++++++++++++++++++++++-------
 target/arm/machine.c                   |  2 +-
 target/arm/op_helper.c                 |  9 +----
 target/arm/translate-a64.c             | 12 ++++++
 19 files changed, 164 insertions(+), 55 deletions(-)

Re: [PULL v2 00/11] target-arm queue

[Peter Maydell]

On Thu, 11 Feb 2021 at 19:57, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
> ethernet device failed 'make check' on big-endian hosts.
>
> -- PMM
>
> The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
>
>   Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
>
> for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
>
>   target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Correctly initialize MDCR_EL2.HPMN
>  * versal: Use nr_apu_cpus in favor of hard coding 2
>  * accel/tcg: Add URL of clang bug to comment about our workaround
>  * Add support for FEAT_DIT, Data Independent Timing
>  * Remove GPIO from unimplemented NPCM7XX
>  * Fix SCR RES1 handling
>  * Don't migrate CPUARMState.features


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.

-- PMM