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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id h18sm5547186wmm.30.2021.02.14.10.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:04 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 22/42] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword) Date: Sun, 14 Feb 2021 18:58:52 +0100 Message-Id: <20210214175912.732946-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the PINTEH opcode (Parallel Interleave Even Halfword). Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 1 + target/mips/tx79_translate.c | 45 ++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 653910371d2..fbd2be569ad 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -57,6 +57,7 @@ PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd # MMI3 +PINTEH 011100 ..... ..... ..... 01010 101001 @rs_rt_rd PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index ac75d95b82b..47d84c465a2 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -638,3 +638,48 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) return true; } + +/* Parallel Interleave Even Halfword */ +static bool trans_PINTEH(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 ax, bx; + + if (a->rd == 0) { + /* nop */ + return true; + } + + if (unlikely(a->rs == 0 && a->rt == 0)) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + return true; + } + + ax = tcg_temp_new_i64(); + bx = tcg_temp_new_i64(); + + /* Lower halve */ + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + if (a->rd != a->rt) { + tcg_gen_mov_i64(cpu_gpr[a->rd], bx); + } + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 16, 16); + tcg_gen_shri_i64(ax, ax, 32); + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 48, 16); + + /* Upper halve */ + gen_load_gpr_hi(ax, a->rs); + gen_load_gpr_hi(bx, a->rt); + if (a->rd != a->rt) { + tcg_gen_mov_i64(cpu_gpr_hi[a->rd], bx); + } + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 16, 16); + tcg_gen_shri_i64(ax, ax, 32); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 48, 16); + + tcg_temp_free(bx); + tcg_temp_free(ax); + + return true; +} -- 2.26.2