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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id d15sm16117354wru.80.2021.02.14.10.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:24 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 26/42] target/mips/tx79: Introduce SQ opcode (Store Quadword) Date: Sun, 14 Feb 2021 18:58:56 +0100 Message-Id: <20210214175912.732946-27-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the SQ opcode (Store Quadword). Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 1 + target/mips/tx79_translate.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index b5396f48c2d..f1cb7ebfa3c 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -73,3 +73,4 @@ PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd # SPECIAL LQ 011110 ..... ..... ................ @ldst +SQ 011111 ..... ..... ................ @ldst diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 293efd7bd06..386bae7808b 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -411,6 +411,33 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a) return true; } +static bool trans_SQ(DisasContext *ctx, arg_itype *a) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv addr = tcg_temp_new(); + + gen_base_offset_addr(ctx, addr, a->base, a->offset); + /* + * Clear least-significant four bits of the effective + * address, effectively creating an aligned address. + */ + tcg_gen_andi_tl(addr, addr, ~0xf); + + /* Lower halve */ + gen_load_gpr(t0, a->rt); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); + + /* Upper halve */ + tcg_gen_addi_i64(addr, addr, 8); + gen_load_gpr_hi(t0, a->rt); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); + + tcg_temp_free(addr); + tcg_temp_free(t0); + + return true; +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- -- 2.26.2