From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Taylor Simpson" <tsimpson@quicinc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 15/35] Hexagon (target/hexagon) instruction printing
Date: Wed, 17 Feb 2021 15:40:03 -0800 [thread overview]
Message-ID: <20210217234023.1742406-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210217234023.1742406-1-richard.henderson@linaro.org>
From: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1612763186-18161-15-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/printinsn.h | 27 +++++++
target/hexagon/printinsn.c | 146 +++++++++++++++++++++++++++++++++++++
2 files changed, 173 insertions(+)
create mode 100644 target/hexagon/printinsn.h
create mode 100644 target/hexagon/printinsn.c
diff --git a/target/hexagon/printinsn.h b/target/hexagon/printinsn.h
new file mode 100644
index 0000000000..2ecd1731d0
--- /dev/null
+++ b/target/hexagon/printinsn.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_PRINTINSN_H
+#define HEXAGON_PRINTINSN_H
+
+#include "insn.h"
+
+void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
+ target_ulong pc);
+void snprint_a_pkt_debug(GString *buf, Packet *pkt);
+
+#endif
diff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c
new file mode 100644
index 0000000000..4865cdd133
--- /dev/null
+++ b/target/hexagon/printinsn.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "attribs.h"
+#include "printinsn.h"
+#include "insn.h"
+#include "reg_fields.h"
+#include "internal.h"
+
+static const char *sreg2str(unsigned int reg)
+{
+ if (reg < TOTAL_PER_THREAD_REGS) {
+ return hexagon_regnames[reg];
+ } else {
+ return "???";
+ }
+}
+
+static const char *creg2str(unsigned int reg)
+{
+ return sreg2str(reg + HEX_REG_SA0);
+}
+
+static void snprintinsn(GString *buf, Insn *insn)
+{
+ switch (insn->opcode) {
+#define DEF_VECX_PRINTINFO(TAG, FMT, ...) DEF_PRINTINFO(TAG, FMT, __VA_ARGS__)
+#define DEF_PRINTINFO(TAG, FMT, ...) \
+ case TAG: \
+ g_string_append_printf(buf, FMT, __VA_ARGS__); \
+ break;
+#include "printinsn_generated.h.inc"
+#undef DEF_VECX_PRINTINFO
+#undef DEF_PRINTINFO
+ }
+}
+
+void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
+ target_ulong pc)
+{
+ bool has_endloop0 = false;
+ bool has_endloop1 = false;
+ bool has_endloop01 = false;
+
+ for (int i = 0; i < pkt->num_insns; i++) {
+ if (pkt->insn[i].part1) {
+ continue;
+ }
+
+ /* We'll print the endloop's at the end of the packet */
+ if (pkt->insn[i].opcode == J2_endloop0) {
+ has_endloop0 = true;
+ continue;
+ }
+ if (pkt->insn[i].opcode == J2_endloop1) {
+ has_endloop1 = true;
+ continue;
+ }
+ if (pkt->insn[i].opcode == J2_endloop01) {
+ has_endloop01 = true;
+ continue;
+ }
+
+ g_string_append_printf(buf, "0x" TARGET_FMT_lx "\t", words[i]);
+
+ if (i == 0) {
+ g_string_append(buf, "{");
+ }
+
+ g_string_append(buf, "\t");
+ snprintinsn(buf, &(pkt->insn[i]));
+
+ if (i < pkt->num_insns - 1) {
+ /*
+ * Subinstructions are two instructions encoded
+ * in the same word. Print them on the same line.
+ */
+ if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN)) {
+ g_string_append(buf, "; ");
+ snprintinsn(buf, &(pkt->insn[i + 1]));
+ i++;
+ } else if (pkt->insn[i + 1].opcode != J2_endloop0 &&
+ pkt->insn[i + 1].opcode != J2_endloop1 &&
+ pkt->insn[i + 1].opcode != J2_endloop01) {
+ pc += 4;
+ g_string_append_printf(buf, "\n0x" TARGET_FMT_lx ": ", pc);
+ }
+ }
+ }
+ g_string_append(buf, " }");
+ if (has_endloop0) {
+ g_string_append(buf, " :endloop0");
+ }
+ if (has_endloop1) {
+ g_string_append(buf, " :endloop1");
+ }
+ if (has_endloop01) {
+ g_string_append(buf, " :endloop01");
+ }
+}
+
+void snprint_a_pkt_debug(GString *buf, Packet *pkt)
+{
+ int slot, opcode;
+
+ if (pkt->num_insns > 1) {
+ g_string_append(buf, "\n{\n");
+ }
+
+ for (int i = 0; i < pkt->num_insns; i++) {
+ if (pkt->insn[i].part1) {
+ continue;
+ }
+ g_string_append(buf, "\t");
+ snprintinsn(buf, &(pkt->insn[i]));
+
+ if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN)) {
+ g_string_append(buf, " //subinsn");
+ }
+ if (pkt->insn[i].extension_valid) {
+ g_string_append(buf, " //constant extended");
+ }
+ slot = pkt->insn[i].slot;
+ opcode = pkt->insn[i].opcode;
+ g_string_append_printf(buf, " //slot=%d:tag=%s\n",
+ slot, opcode_names[opcode]);
+ }
+ if (pkt->num_insns > 1) {
+ g_string_append(buf, "}\n");
+ }
+}
--
2.25.1
next prev parent reply other threads:[~2021-02-17 23:49 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-17 23:39 [PULL 00/35] hexagon initial commit Richard Henderson
2021-02-17 23:39 ` [PULL 01/35] qemu/int128: Add int128_or Richard Henderson
2021-02-17 23:39 ` [PULL 02/35] Hexagon Update MAINTAINERS file Richard Henderson
2021-02-17 23:39 ` [PULL 03/35] Hexagon (target/hexagon) README Richard Henderson
2021-02-17 23:39 ` [PULL 04/35] Hexagon (include/elf.h) ELF machine definition Richard Henderson
2021-02-17 23:39 ` [PULL 05/35] Hexagon (target/hexagon) scalar core definition Richard Henderson
2021-02-17 23:39 ` [PULL 06/35] Hexagon (disas) disassembler Richard Henderson
2021-08-09 11:12 ` Peter Maydell
2021-02-17 23:39 ` [PULL 07/35] Hexagon (target/hexagon) register names Richard Henderson
2021-02-17 23:39 ` [PULL 08/35] Hexagon (target/hexagon) scalar core helpers Richard Henderson
2021-02-17 23:39 ` [PULL 09/35] Hexagon (target/hexagon) GDB Stub Richard Henderson
2021-02-17 23:39 ` [PULL 10/35] Hexagon (target/hexagon) architecture types Richard Henderson
2021-02-17 23:39 ` [PULL 11/35] Hexagon (target/hexagon) instruction and packet types Richard Henderson
2021-02-17 23:40 ` [PULL 12/35] Hexagon (target/hexagon) register fields Richard Henderson
2021-02-17 23:40 ` [PULL 13/35] Hexagon (target/hexagon) instruction attributes Richard Henderson
2021-02-17 23:40 ` [PULL 14/35] Hexagon (target/hexagon) instruction/packet decode Richard Henderson
2021-02-17 23:40 ` Richard Henderson [this message]
2021-02-17 23:40 ` [PULL 16/35] Hexagon (target/hexagon/arch.[ch]) utility functions Richard Henderson
2021-02-17 23:40 ` [PULL 17/35] Hexagon (target/hexagon/conv_emu.[ch]) " Richard Henderson
2021-02-17 23:40 ` [PULL 18/35] Hexagon (target/hexagon/fma_emu.[ch]) " Richard Henderson
2021-02-17 23:40 ` [PULL 19/35] Hexagon (target/hexagon/imported) arch import Richard Henderson
2021-02-17 23:40 ` [PULL 20/35] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Richard Henderson
2021-02-17 23:40 ` [PULL 21/35] Hexagon (target/hexagon) generator phase 2 - generate header files Richard Henderson
2021-02-17 23:40 ` [PULL 22/35] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Richard Henderson
2021-02-17 23:40 ` [PULL 23/35] Hexagon (target/hexagon) generater phase 4 - " Richard Henderson
2021-02-17 23:40 ` [PULL 24/35] Hexagon (target/hexagon) opcode data structures Richard Henderson
2021-02-17 23:40 ` [PULL 25/35] Hexagon (target/hexagon) macros Richard Henderson
2021-02-17 23:40 ` [PULL 26/35] Hexagon (target/hexagon) instruction classes Richard Henderson
2021-02-17 23:40 ` [PULL 27/35] Hexagon (target/hexagon) TCG generation Richard Henderson
2021-02-17 23:40 ` [PULL 28/35] Hexagon (target/hexagon) TCG for instructions with multiple definitions Richard Henderson
2021-02-17 23:40 ` [PULL 29/35] Hexagon (target/hexagon) TCG for floating point instructions Richard Henderson
2021-02-17 23:40 ` [PULL 30/35] Hexagon (target/hexagon) translation Richard Henderson
2021-02-17 23:40 ` [PULL 31/35] Hexagon (linux-user/hexagon) Linux user emulation Richard Henderson
2021-02-17 23:40 ` [PULL 32/35] Hexagon (tests/tcg/hexagon) TCG tests - multiarch Richard Henderson
2021-02-17 23:40 ` [PULL 33/35] Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc Richard Henderson
2021-02-17 23:40 ` [PULL 34/35] Hexagon (tests/tcg/hexagon) TCG tests - floating point Richard Henderson
2021-02-17 23:40 ` [PULL 35/35] Hexagon build infrastructure Richard Henderson
2021-02-18 0:19 ` [PULL 00/35] hexagon initial commit no-reply
2021-02-18 11:20 ` Peter Maydell
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