From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Taylor Simpson <tsimpson@quicinc.com>
Subject: [PULL 29/35] Hexagon (target/hexagon) TCG for floating point instructions
Date: Wed, 17 Feb 2021 15:40:17 -0800 [thread overview]
Message-ID: <20210217234023.1742406-30-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210217234023.1742406-1-richard.henderson@linaro.org>
From: Taylor Simpson <tsimpson@quicinc.com>
The imported code uses host floating point. We override them
to use qemu softfloat
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1612763186-18161-29-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/gen_tcg.h | 121 +++++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index a8d9321b42..e044deaff2 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -195,4 +195,125 @@
#define fGEN_TCG_S4_stored_locked(SHORTCODE) \
do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
+/* Floating point */
+#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
+ gen_helper_conv_sf2df(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
+ gen_helper_conv_df2sf(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
+ gen_helper_conv_uw2sf(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
+ gen_helper_conv_uw2df(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
+ gen_helper_conv_w2sf(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
+ gen_helper_conv_w2df(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
+ gen_helper_conv_ud2sf(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
+ gen_helper_conv_ud2df(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
+ gen_helper_conv_d2sf(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
+ gen_helper_conv_d2df(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
+ gen_helper_conv_sf2uw(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
+ gen_helper_conv_sf2w(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
+ gen_helper_conv_sf2ud(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
+ gen_helper_conv_sf2d(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
+ gen_helper_conv_df2uw(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
+ gen_helper_conv_df2w(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
+ gen_helper_conv_df2ud(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
+ gen_helper_conv_df2d(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
+ gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
+ gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
+ gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
+ gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
+ gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
+ gen_helper_conv_df2w_chop(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
+ gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
+ gen_helper_conv_df2d_chop(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_sfadd(SHORTCODE) \
+ gen_helper_sfadd(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfsub(SHORTCODE) \
+ gen_helper_sfsub(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
+ gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
+ gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
+ gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
+ gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfmax(SHORTCODE) \
+ gen_helper_sfmax(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfmin(SHORTCODE) \
+ gen_helper_sfmin(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfclass(SHORTCODE) \
+ do { \
+ TCGv imm = tcg_const_tl(uiV); \
+ gen_helper_sfclass(PdV, cpu_env, RsV, imm); \
+ tcg_temp_free(imm); \
+ } while (0)
+#define fGEN_TCG_F2_sffixupn(SHORTCODE) \
+ gen_helper_sffixupn(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sffixupd(SHORTCODE) \
+ gen_helper_sffixupd(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sffixupr(SHORTCODE) \
+ gen_helper_sffixupr(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_dfadd(SHORTCODE) \
+ gen_helper_dfadd(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfsub(SHORTCODE) \
+ gen_helper_dfsub(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfmax(SHORTCODE) \
+ gen_helper_dfmax(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfmin(SHORTCODE) \
+ gen_helper_dfmin(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
+ gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
+ gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
+ gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
+ gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfclass(SHORTCODE) \
+ do { \
+ TCGv imm = tcg_const_tl(uiV); \
+ gen_helper_dfclass(PdV, cpu_env, RssV, imm); \
+ tcg_temp_free(imm); \
+ } while (0)
+#define fGEN_TCG_F2_sfmpy(SHORTCODE) \
+ gen_helper_sfmpy(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sffma(SHORTCODE) \
+ gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV)
+#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
+ gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV)
+#define fGEN_TCG_F2_sffms(SHORTCODE) \
+ gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV)
+#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
+ gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV)
+#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
+ gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV)
+
+#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
+ gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
+ gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
+
#endif
--
2.25.1
next prev parent reply other threads:[~2021-02-18 0:03 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-17 23:39 [PULL 00/35] hexagon initial commit Richard Henderson
2021-02-17 23:39 ` [PULL 01/35] qemu/int128: Add int128_or Richard Henderson
2021-02-17 23:39 ` [PULL 02/35] Hexagon Update MAINTAINERS file Richard Henderson
2021-02-17 23:39 ` [PULL 03/35] Hexagon (target/hexagon) README Richard Henderson
2021-02-17 23:39 ` [PULL 04/35] Hexagon (include/elf.h) ELF machine definition Richard Henderson
2021-02-17 23:39 ` [PULL 05/35] Hexagon (target/hexagon) scalar core definition Richard Henderson
2021-02-17 23:39 ` [PULL 06/35] Hexagon (disas) disassembler Richard Henderson
2021-08-09 11:12 ` Peter Maydell
2021-02-17 23:39 ` [PULL 07/35] Hexagon (target/hexagon) register names Richard Henderson
2021-02-17 23:39 ` [PULL 08/35] Hexagon (target/hexagon) scalar core helpers Richard Henderson
2021-02-17 23:39 ` [PULL 09/35] Hexagon (target/hexagon) GDB Stub Richard Henderson
2021-02-17 23:39 ` [PULL 10/35] Hexagon (target/hexagon) architecture types Richard Henderson
2021-02-17 23:39 ` [PULL 11/35] Hexagon (target/hexagon) instruction and packet types Richard Henderson
2021-02-17 23:40 ` [PULL 12/35] Hexagon (target/hexagon) register fields Richard Henderson
2021-02-17 23:40 ` [PULL 13/35] Hexagon (target/hexagon) instruction attributes Richard Henderson
2021-02-17 23:40 ` [PULL 14/35] Hexagon (target/hexagon) instruction/packet decode Richard Henderson
2021-02-17 23:40 ` [PULL 15/35] Hexagon (target/hexagon) instruction printing Richard Henderson
2021-02-17 23:40 ` [PULL 16/35] Hexagon (target/hexagon/arch.[ch]) utility functions Richard Henderson
2021-02-17 23:40 ` [PULL 17/35] Hexagon (target/hexagon/conv_emu.[ch]) " Richard Henderson
2021-02-17 23:40 ` [PULL 18/35] Hexagon (target/hexagon/fma_emu.[ch]) " Richard Henderson
2021-02-17 23:40 ` [PULL 19/35] Hexagon (target/hexagon/imported) arch import Richard Henderson
2021-02-17 23:40 ` [PULL 20/35] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Richard Henderson
2021-02-17 23:40 ` [PULL 21/35] Hexagon (target/hexagon) generator phase 2 - generate header files Richard Henderson
2021-02-17 23:40 ` [PULL 22/35] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Richard Henderson
2021-02-17 23:40 ` [PULL 23/35] Hexagon (target/hexagon) generater phase 4 - " Richard Henderson
2021-02-17 23:40 ` [PULL 24/35] Hexagon (target/hexagon) opcode data structures Richard Henderson
2021-02-17 23:40 ` [PULL 25/35] Hexagon (target/hexagon) macros Richard Henderson
2021-02-17 23:40 ` [PULL 26/35] Hexagon (target/hexagon) instruction classes Richard Henderson
2021-02-17 23:40 ` [PULL 27/35] Hexagon (target/hexagon) TCG generation Richard Henderson
2021-02-17 23:40 ` [PULL 28/35] Hexagon (target/hexagon) TCG for instructions with multiple definitions Richard Henderson
2021-02-17 23:40 ` Richard Henderson [this message]
2021-02-17 23:40 ` [PULL 30/35] Hexagon (target/hexagon) translation Richard Henderson
2021-02-17 23:40 ` [PULL 31/35] Hexagon (linux-user/hexagon) Linux user emulation Richard Henderson
2021-02-17 23:40 ` [PULL 32/35] Hexagon (tests/tcg/hexagon) TCG tests - multiarch Richard Henderson
2021-02-17 23:40 ` [PULL 33/35] Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc Richard Henderson
2021-02-17 23:40 ` [PULL 34/35] Hexagon (tests/tcg/hexagon) TCG tests - floating point Richard Henderson
2021-02-17 23:40 ` [PULL 35/35] Hexagon build infrastructure Richard Henderson
2021-02-18 0:19 ` [PULL 00/35] hexagon initial commit no-reply
2021-02-18 11:20 ` Peter Maydell
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