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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id b6sm10527374wrq.56.2021.02.21.06.34.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Feb 2021 06:34:34 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 00/43] MIPS patches for 2021-02-21 Date: Sun, 21 Feb 2021 15:33:49 +0100 Message-Id: <20210221143432.2468220-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , "Michael S. Tsirkin" , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit a528b8c4c638d60cc474c2f80952ff0f2e60521a= :=0D =0D Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sdmmc-20210220' = into staging (2021-02-20 19:28:27 +0000)=0D =0D are available in the Git repository at:=0D =0D https://gitlab.com/philmd/qemu.git tags/mips-20210221=0D =0D for you to fetch changes up to 98e7c7108127bc9f2bf9065cbddd25778025b9c6:=0D =0D vt82c686: Fix superio_cfg_{read,write}() functions (2021-02-21 15:28:52 += 0100)=0D =0D ----------------------------------------------------------------=0D MIPS patches queue=0D =0D - Drop redundant struct MemmapEntry (Bin)=0D - Fix for Coverity CID 1438965 and 1438967 (Jiaxun)=0D - Add MIPS bootloader API (Jiaxun)=0D - Use MIPS bootloader API on fuloong2e and boston machines (Jiaxun)=0D - Add PMON test for Loongson-3A1000 CPU (Jiaxun)=0D - Convert to translator API (Philippe)=0D - MMU cleanups (Philippe)=0D - Promote 128-bit multimedia registers as global ones (Philippe)=0D - Various cleanups/fixes on the VT82C686B southbridge (Zoltan)=0D ----------------------------------------------------------------=0D =0D BALATON Zoltan (16):=0D vt82c686: Move superio memory region to SuperIOConfig struct=0D vt82c686: Reorganise code=0D vt82c686: Fix SMBus IO base and configuration registers=0D vt82c686: Make vt82c686-pm an I/O tracing region=0D vt82c686: Correct vt82c686-pm I/O size=0D vt82c686: Correctly reset all registers to default values on reset=0D vt82c686: Fix up power management io base and config=0D vt82c686: Set user_creatable=3Dfalse for VT82C686B_PM=0D vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm=0D based on it=0D vt82c686: Simplify vt82c686b_realize()=0D vt82c686: Move creation of ISA devices to the ISA bridge=0D vt82c686: Remove index field of SuperIOConfig=0D vt82c686: Reduce indentation by returning early=0D vt82c686: Simplify by returning earlier=0D vt82c686: Log superio_cfg unimplemented accesses=0D vt82c686: Fix superio_cfg_{read,write}() functions=0D =0D Bin Meng (1):=0D hw/mips: loongson3: Drop 'struct MemmapEntry'=0D =0D Jiaxun Yang (6):=0D hw/mips: Add a bootloader helper=0D hw/mips/fuloong2e: Use bl_gen_kernel_jump to generate bootloaders=0D hw/mips/boston: Use bl_gen_kernel_jump to generate bootloaders=0D hw/mips/boston: Use bootloader helper to set GCRs=0D hw/intc/loongson_liointc: Fix per core ISR handling=0D tests/acceptance: Test PMON with Loongson-3A1000 CPU=0D =0D Philippe Mathieu-Daud=C3=A9 (20):=0D target/mips: fetch code with translator_ld=0D target/mips: Remove access_type argument from map_address() handler=0D target/mips: Remove access_type argument from get_seg_physical_address=0D target/mips: Remove access_type arg from get_segctl_physical_address()=0D target/mips: Remove access_type argument from get_physical_address()=0D target/mips: Remove unused MMU definitions=0D target/mips: Replace magic value by MMU_DATA_LOAD definition=0D target/mips: Let do_translate_address() take MMUAccessType argument=0D target/mips: Let cpu_mips_translate_address() take MMUAccessType arg=0D target/mips: Let raise_mmu_exception() take MMUAccessType argument=0D target/mips: Let get_physical_address() take MMUAccessType argument=0D target/mips: Let get_seg*_physical_address() take MMUAccessType arg=0D target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType=0D target/mips: Remove unused 'rw' argument from page_table_walk_refill()=0D target/mips: Include missing "tcg/tcg.h" header=0D target/mips: Make cpu_HI/LO registers public=0D target/mips: Promote 128-bit multimedia registers as global ones=0D target/mips: Rename 128-bit upper halve GPR registers=0D target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers=0D target/mips: Use GPR move functions in gen_HILO1_tx79()=0D =0D hw/mips/loongson3_bootp.h | 7 +-=0D include/hw/isa/vt82c686.h | 1 +=0D include/hw/mips/bootloader.h | 14 +=0D include/hw/pci/pci_ids.h | 3 +-=0D target/mips/cpu.h | 26 +-=0D target/mips/internal.h | 10 +-=0D target/mips/translate.h | 8 +=0D hw/intc/loongson_liointc.c | 16 +-=0D hw/isa/vt82c686.c | 542 ++++++++++++--------=0D hw/mips/bootloader.c | 200 ++++++++=0D hw/mips/boston.c | 62 +--=0D hw/mips/fuloong2e.c | 60 +--=0D hw/mips/loongson3_virt.c | 6 +-=0D target/mips/msa_helper.c | 1 +=0D target/mips/op_helper.c | 9 +-=0D target/mips/tlb_helper.c | 80 ++-=0D target/mips/translate.c | 111 ++--=0D MAINTAINERS | 1 +=0D hw/isa/trace-events | 2 +=0D hw/mips/meson.build | 2 +-=0D tests/acceptance/machine_mips_loongson3v.py | 39 ++=0D 21 files changed, 741 insertions(+), 459 deletions(-)=0D create mode 100644 include/hw/mips/bootloader.h=0D create mode 100644 hw/mips/bootloader.c=0D create mode 100644 tests/acceptance/machine_mips_loongson3v.py=0D =0D -- =0D 2.26.2=0D =0D