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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id u23sm2721526ljd.28.2021.02.23.00.58.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 00:58:58 -0800 (PST) Date: Tue, 23 Feb 2021 09:58:57 +0100 From: "Edgar E. Iglesias" To: Bin Meng Subject: Re: [PATCH v4 2/5] hw/arm: xlnx-zynqmp: Clean up coding convention issues Message-ID: <20210223085857.GR477672@toto> References: <20210222130514.2167-1-bmeng.cn@gmail.com> <20210222130514.2167-3-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210222130514.2167-3-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Xuzhou Cheng , Bin Meng , qemu-devel@nongnu.org, Francisco Iglesias , qemu-arm@nongnu.org, Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Feb 22, 2021 at 09:05:11PM +0800, Bin Meng wrote: > From: Xuzhou Cheng > > There are some coding convention warnings in xlnx-zynqmp.c and > xlnx-zynqmp.h, as reported by: > > $ ./scripts/checkpatch.pl include/hw/arm/xlnx-zynqmp.h > $ ./scripts/checkpatch.pl hw/arm/xlnx-zynqmp.c > > Let's clean them up. > > Signed-off-by: Xuzhou Cheng > Signed-off-by: Bin Meng Reviewed-by: Edgar E. Iglesias > > --- > > Changes in v4: > - remove one change that is not a checkpatch warning > > include/hw/arm/xlnx-zynqmp.h | 3 ++- > hw/arm/xlnx-zynqmp.c | 9 ++++++--- > 2 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h > index 6f45387a17..be15cc8814 100644 > --- a/include/hw/arm/xlnx-zynqmp.h > +++ b/include/hw/arm/xlnx-zynqmp.h > @@ -60,7 +60,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) > > #define XLNX_ZYNQMP_GIC_REGIONS 6 > > -/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets > +/* > + * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets > * and under-decodes the 64k region. This mirrors the 4k regions to every 4k > * aligned address in the 64k region. To implement each GIC region needs a > * number of memory region aliases. > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index 881847255b..49465a2794 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -301,11 +301,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > > ram_size = memory_region_size(s->ddr_ram); > > - /* Create the DDR Memory Regions. User friendly checks should happen at > + /* > + * Create the DDR Memory Regions. User friendly checks should happen at > * the board level > */ > if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { > - /* The RAM size is above the maximum available for the low DDR. > + /* > + * The RAM size is above the maximum available for the low DDR. > * Create the high DDR memory region as well. > */ > assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); > @@ -526,7 +528,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); > Object *sdhci = OBJECT(&s->sdhci[i]); > > - /* Compatible with: > + /* > + * Compatible with: > * - SD Host Controller Specification Version 3.00 > * - SDIO Specification Version 3.0 > * - eMMC Specification Version 4.51 > -- > 2.25.1 >