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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id w26sm2488555lfr.186.2021.02.23.01.33.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 01:33:06 -0800 (PST) Date: Tue, 23 Feb 2021 10:33:06 +0100 From: "Edgar E. Iglesias" To: Bin Meng Subject: Re: [PATCH v4 1/5] hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA model Message-ID: <20210223093306.GX477672@toto> References: <20210222130514.2167-1-bmeng.cn@gmail.com> <20210222130514.2167-2-bmeng.cn@gmail.com> <20210223092127.GU477672@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Xuzhou Cheng , Bin Meng , "qemu-devel@nongnu.org Developers" , Francisco Iglesias , qemu-arm , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Feb 23, 2021 at 05:23:43PM +0800, Bin Meng wrote: > Hi Edgar, > > On Tue, Feb 23, 2021 at 5:21 PM Edgar E. Iglesias > wrote: > > > > On Mon, Feb 22, 2021 at 09:05:10PM +0800, Bin Meng wrote: > > > From: Xuzhou Cheng > > > > > > ZynqMP QSPI supports SPI transfer using DMA mode, but currently this > > > is unimplemented. When QSPI is programmed to use DMA mode, QEMU will > > > crash. This is observed when testing VxWorks 7. > > > > > > This adds a Xilinx CSU DMA model and the implementation is based on > > > https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c. > > > The DST part of the model is verified along with ZynqMP GQSPI model. > > > > > > Signed-off-by: Xuzhou Cheng > > > Signed-off-by: Bin Meng > > > > > > --- > > > > > > Changes in v4: > > > - Add complete CSU DMA model based on Edgar's branch > > > - Differences with Edgar's branch: > > > 1. Match the registers' FIELD to UG1807. > > > 2. Remove "byte-align" property. Per UG1807, SIZE and ADDR registers > > > must be word aligned. > > > > The relaxation of alignment is a new feature, not included on the ZynqMP but > > it will be included in future versions. Would be nice to keep it but we can > > also add it later since it's not really related to QSPI. > > I think Xilinx folks can add the "byte-align" property in the future > patches. Is this a new feature for Versal? It's not in silicon yet, yeah, we can add it later. > > > > > > 3. Make the values of int_enable and int_disable mutually exclusive > > > otherwise IRQ cannot be delivered. > > > > This doesn't sound right. The enable and disable regs are stateless. > > They both indirectly modify the MASK register. > > > > I.e, setting a bit in the enable register will clear the correspoding bit in the > > mask register, atomically, without the need for read-modify-write of MASK. > > > > The disable register does the opposite. > > > > > 4. Clear int_status after int_disable is set. > > > > This doesn't sound right either. Status is a w1c register, i.e bits get set > > when the interrupt event happens in the DMA and bits only get cleared when > > SW writes a 1 to the STATUS reg to clear bits (write one to clear, w1c). > > > > Other than the interrupt issues, I think this looks good. > > Without these interrupt fixes, our tests cannot pass. We will have a > further look at your comments. This is a common interrupt handling pattern in most Xilinx devices. You can look at the xlnx-zdma.c IMR, ISR, IEN, IDS regs as an example. Cheers, Edgar