From: Andrew Jeffery <andrew@aj.id.au>
To: qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, ryan_chen@aspeedtech.com,
minyard@acm.org, qemu-devel@nongnu.org, clg@kaod.org,
joel@jms.id.au
Subject: [PATCH 1/4] arm: ast2600: Force a multiple of 32 of IRQs for the GIC
Date: Fri, 26 Feb 2021 17:27:55 +1030 [thread overview]
Message-ID: <20210226065758.547824-2-andrew@aj.id.au> (raw)
In-Reply-To: <20210226065758.547824-1-andrew@aj.id.au>
This appears to be a requirement of the GIC model. The AST2600 allocates
197 GIC IRQs, which we will adjust shortly.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
hw/arm/aspeed_ast2600.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index bf31ca351feb..bc0eeb058b24 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
#define ASPEED_A7MPCORE_ADDR 0x40460000
-#define ASPEED_SOC_AST2600_MAX_IRQ 128
+#define AST2600_MAX_IRQ 128
/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2600_irqmap[] = {
@@ -267,7 +267,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
&error_abort);
object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
- ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
+ ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
--
2.27.0
next prev parent reply other threads:[~2021-02-26 7:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-26 6:57 [PATCH 0/4] aspeed: LPC peripheral controller devices Andrew Jeffery
2021-02-26 6:57 ` Andrew Jeffery [this message]
2021-02-26 8:56 ` [PATCH 1/4] arm: ast2600: Force a multiple of 32 of IRQs for the GIC Philippe Mathieu-Daudé
2021-02-28 23:07 ` Andrew Jeffery
2021-03-01 0:23 ` Andrew Jeffery
2021-02-26 6:57 ` [PATCH 2/4] arm: ast2600: Fix iBT IRQ ID Andrew Jeffery
2021-02-26 8:58 ` Philippe Mathieu-Daudé
2021-02-28 23:08 ` Andrew Jeffery
2021-02-26 6:57 ` [PATCH 3/4] hw/misc: Add a basic Aspeed LPC controller model Andrew Jeffery
2021-02-26 6:57 ` [PATCH 4/4] hw/misc: Model KCS devices in the Aspeed LPC controller Andrew Jeffery
2021-02-26 9:51 ` Cédric Le Goater
2021-02-28 23:14 ` Andrew Jeffery
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