From: Andrew Jeffery <andrew@aj.id.au>
To: qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, ryan_chen@aspeedtech.com,
minyard@acm.org, qemu-devel@nongnu.org, f4bug@amsat.org,
clg@kaod.org, joel@jms.id.au
Subject: [PATCH v2 2/5] hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet
Date: Mon, 1 Mar 2021 11:36:07 +1030 [thread overview]
Message-ID: <20210301010610.355702-3-andrew@aj.id.au> (raw)
In-Reply-To: <20210301010610.355702-1-andrew@aj.id.au>
The datasheet says we have 197 IRQs allocated, and we need more than 128
to describe IRQs from LPC devices. Raise the value now to allow
modelling of the LPC devices.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
hw/arm/aspeed_ast2600.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index bc0eeb058b24..22fcb5b0edbe 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
#define ASPEED_A7MPCORE_ADDR 0x40460000
-#define AST2600_MAX_IRQ 128
+#define AST2600_MAX_IRQ 197
/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2600_irqmap[] = {
--
2.27.0
next prev parent reply other threads:[~2021-03-01 1:08 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-01 1:06 [PATCH v2 0/5] aspeed: LPC peripheral controller devices Andrew Jeffery
2021-03-01 1:06 ` [PATCH v2 1/5] arm: ast2600: Force a multiple of 32 of IRQs for the GIC Andrew Jeffery
2021-03-01 1:06 ` Andrew Jeffery [this message]
2021-03-01 7:59 ` [PATCH v2 2/5] hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet Philippe Mathieu-Daudé
2021-03-01 10:35 ` Cédric Le Goater
2023-10-26 4:32 ` Philippe Mathieu-Daudé
2021-03-01 1:06 ` [PATCH v2 3/5] hw/arm: ast2600: Correct the iBT interrupt ID Andrew Jeffery
2021-03-01 8:00 ` Philippe Mathieu-Daudé
2021-03-01 10:35 ` Cédric Le Goater
2021-03-01 1:06 ` [PATCH v2 4/5] hw/misc: Add a basic Aspeed LPC controller model Andrew Jeffery
2021-03-01 21:46 ` Andrew Jeffery
2021-03-01 1:06 ` [PATCH v2 5/5] hw/misc: Model KCS devices in the Aspeed LPC controller Andrew Jeffery
2021-03-01 10:41 ` Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210301010610.355702-3-andrew@aj.id.au \
--to=andrew@aj.id.au \
--cc=clg@kaod.org \
--cc=f4bug@amsat.org \
--cc=joel@jms.id.au \
--cc=minyard@acm.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=ryan_chen@aspeedtech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).