From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Sarah Harris" <S.E.Harris@kent.ac.uk>,
"Chris Wulff" <crwulff@gmail.com>,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
"David Hildenbrand" <david@redhat.com>,
"Anthony Green" <green@moxielogic.com>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Thomas Huth" <thuth@redhat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Max Filippov" <jcmvbkbc@gmail.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Guan Xuetao" <gxt@mprc.pku.edu.cn>,
"Marek Vasut" <marex@denx.de>,
"Yoshinori Sato" <ysato@users.sourceforge.jp>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Claudio Fontana" <cfontana@suse.de>,
qemu-ppc@nongnu.org, "Artyom Tarasenko" <atar4qemu@gmail.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Greg Kurz" <groug@kaod.org>,
qemu-s390x@nongnu.org, qemu-arm@nongnu.org,
"Michael Rolnik" <mrolnik@gmail.com>,
"Stafford Horne" <shorne@gmail.com>,
"David Gibson" <david@gibson.dropbear.id.au>,
qemu-riscv@nongnu.org,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Cornelia Huck" <cohuck@redhat.com>,
"Laurent Vivier" <laurent@vivier.eu>,
"Michael Walle" <michael@walle.cc>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 12/17] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
Date: Mon, 1 Mar 2021 22:51:05 +0100 [thread overview]
Message-ID: <20210301215110.772346-13-f4bug@amsat.org> (raw)
In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
5 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 0a2c29c3735..6713a615916 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -108,8 +108,6 @@ struct AccelCPUClass;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
- * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -151,7 +149,6 @@ struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
- int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 60c667801ef..3c3f211136d 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
+ */
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
/**
* @get_crash_info: Callback for reporting guest crash information in
* GUEST_PANICKED events.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c74390aafbf..c44229205ff 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
CPUClass *cc = CPU_GET_CLASS(cpu);
int ret = 0;
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
+ if (cc->sysemu_ops->asidx_from_attrs) {
+ ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
assert(ret < cpu->num_ases && ret >= 0);
}
return ret;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7dc6956f2cc..acaa3ab68da 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
@@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
- cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b26905b22a3..10884540610 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
.write_elf64_note = x86_cpu_write_elf64_note,
@@ -7429,7 +7430,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.2
next prev parent reply other threads:[~2021-03-01 22:06 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-01 21:50 [PATCH v2 00/17] cpu: Introduce SysemuCPUOps structure Philippe Mathieu-Daudé
2021-03-01 21:50 ` [PATCH v2 01/17] target: Set CPUClass::vmsd instead of DeviceClass::vmsd Philippe Mathieu-Daudé
2021-03-01 21:50 ` [PATCH v2 02/17] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Philippe Mathieu-Daudé
2021-03-01 21:50 ` [PATCH v2 03/17] cpu: Introduce cpu_virtio_is_big_endian() Philippe Mathieu-Daudé
2021-03-01 21:50 ` [PATCH v2 04/17] cpu: Directly use cpu_write_elf*() fallback handlers in place Philippe Mathieu-Daudé
2021-03-01 21:50 ` [PATCH v2 05/17] cpu: Directly use get_paging_enabled() " Philippe Mathieu-Daudé
2021-03-01 21:50 ` [PATCH v2 06/17] cpu: Directly use get_memory_mapping() " Philippe Mathieu-Daudé
2021-03-01 21:51 ` [PATCH v2 07/17] cpu: Introduce SysemuCPUOps structure Philippe Mathieu-Daudé
2021-03-01 21:51 ` [PATCH v2 08/17] cpu: Move CPUClass::vmsd to SysemuCPUOps Philippe Mathieu-Daudé
2021-03-01 21:51 ` [PATCH v2 09/17] cpu: Move CPUClass::virtio_is_big_endian " Philippe Mathieu-Daudé
2021-03-01 21:51 ` [PATCH v2 10/17] cpu: Move CPUClass::get_crash_info " Philippe Mathieu-Daudé
2021-03-01 21:51 ` [PATCH v2 11/17] cpu: Move CPUClass::write_elf* " Philippe Mathieu-Daudé
2021-03-01 21:51 ` Philippe Mathieu-Daudé [this message]
2021-03-01 21:51 ` [PATCH v2 13/17] cpu: Move CPUClass::get_phys_page_debug " Philippe Mathieu-Daudé
2021-03-01 21:51 ` [PATCH v2 14/17] cpu: Move CPUClass::get_memory_mapping " Philippe Mathieu-Daudé
2021-03-01 21:51 ` [PATCH v2 15/17] cpu: Move CPUClass::get_paging_enabled " Philippe Mathieu-Daudé
2021-03-01 21:51 ` [PATCH v2 16/17] cpu: Restrict cpu_paging_enabled / cpu_get_memory_mapping to sysemu Philippe Mathieu-Daudé
2021-03-02 12:34 ` Claudio Fontana
2021-03-02 12:39 ` Philippe Mathieu-Daudé
2021-03-01 21:51 ` [RFC PATCH v2 17/17] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c Philippe Mathieu-Daudé
2021-03-02 7:34 ` Philippe Mathieu-Daudé
2021-03-02 12:35 ` [PATCH v2 00/17] cpu: Introduce SysemuCPUOps structure Claudio Fontana
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