From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Xuzhou Cheng <xuzhou.cheng@windriver.com>,
Bin Meng <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Francisco Iglesias <francisco.iglesias@xilinx.com>,
qemu-arm <qemu-arm@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v6 1/5] hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA model
Date: Tue, 2 Mar 2021 16:19:53 +0100 [thread overview]
Message-ID: <20210302151953.GA477672@toto> (raw)
In-Reply-To: <CAEUhbmVeha7EOjz-q-y+cihL_TG1Afz-M4Go9eBTD0g4JcDgOw@mail.gmail.com>
On Tue, Mar 02, 2021 at 11:16:10PM +0800, Bin Meng wrote:
> Hi Edgar,
Hi Bin,
>
> On Tue, Mar 2, 2021 at 11:03 PM Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> >
> > On Mon, Mar 01, 2021 at 09:20:07PM +0800, Bin Meng wrote:
> > > From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
> > >
> > > ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
....
> > The 3 DONE_CNT bits in R_STATUS need to be w1c so that SW can clear the counter.
> >
> > .w1c = R_STATUS_DONE_CNT_MASK, \
> >
> >
> > For reference, I'm attaching the complete diff I used to pass the testsuite:
> >
>
> Thanks for the review and testing. We will incorporate your diff, test
> and send v7.
>
> Should we include your SoB tag for the diff?
If you take the changes as from my example, you can include:
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Thanks & Best regards,
Edgar
next prev parent reply other threads:[~2021-03-02 15:25 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-01 13:20 [PATCH v6 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI Bin Meng
2021-03-01 13:20 ` [PATCH v6 1/5] hw/dma: xlnx_csu_dma: Implement a Xilinx CSU DMA model Bin Meng
2021-03-02 15:03 ` Edgar E. Iglesias
2021-03-02 15:16 ` Bin Meng
2021-03-02 15:19 ` Edgar E. Iglesias [this message]
2021-03-02 15:21 ` Bin Meng
2021-03-01 13:20 ` [PATCH v6 2/5] hw/arm: xlnx-zynqmp: Clean up coding convention issues Bin Meng
2021-03-01 13:20 ` [PATCH v6 3/5] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI Bin Meng
2021-03-01 13:20 ` [PATCH v6 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues Bin Meng
2021-03-01 13:20 ` [PATCH v6 5/5] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips Bin Meng
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