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Tue, 02 Mar 2021 09:29:49 -0800 (PST) Received: from localhost.localdomain ([45.115.91.0]) by smtp.gmail.com with ESMTPSA id b15sm20122999pgj.84.2021.03.02.09.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 09:29:49 -0800 (PST) From: G S Niteesh Babu To: qemu-devel@nongnu.org Subject: [PATCH 3/3] hw/gpio/avr_gpio.c: add tracing for read and writes Date: Tue, 2 Mar 2021 22:59:19 +0530 Message-Id: <20210302172919.7923-3-niteesh.gs@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210302172919.7923-1-niteesh.gs@gmail.com> References: <20210302172919.7923-1-niteesh.gs@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=niteesh.gs@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: G S Niteesh Babu , f4bug@amsat.org, heecheol.yang@outlook.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Added tracing for gpio read, write, and update output irq. 1) trace_avr_gpio_update_ouput_irq 2) trace_avr_gpio_read 3) trace_avr_gpio_write Signed-off-by: G S Niteesh Babu --- hw/gpio/avr_gpio.c | 16 ++++++++++++---- hw/gpio/trace-events | 6 ++++++ 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c index 7984843841..5c0d6aa922 100644 --- a/hw/gpio/avr_gpio.c +++ b/hw/gpio/avr_gpio.c @@ -25,6 +25,7 @@ #include "hw/irq.h" #include "hw/gpio/avr_gpio.h" #include "hw/qdev-properties.h" +#include "trace.h" static void avr_gpio_reset(DeviceState *dev) { @@ -48,6 +49,7 @@ static void avr_gpio_write_port(AVRGPIOState *s, uint64_t value) if (cur_ddr_pin_val && (cur_port_pin_val != new_port_pin_val)) { qemu_set_irq(s->out[pin], new_port_pin_val); + trace_avr_gpio_update_output_irq(pin, new_port_pin_val); } cur_port_val >>= 1u; cur_ddr_val >>= 1u; @@ -57,19 +59,25 @@ static void avr_gpio_write_port(AVRGPIOState *s, uint64_t value) } static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned int size) { + uint8_t val = 0; AVRGPIOState *s = (AVRGPIOState *)opaque; switch (offset) { case GPIO_PIN: - return s->reg.pin; + val = s->reg.pin; + break; case GPIO_DDR: - return s->reg.ddr; + val = s->reg.ddr; + break; case GPIO_PORT: - return s->reg.port; + val = s->reg.port; + break; default: g_assert_not_reached(); break; } - return 0; + + trace_avr_gpio_read(offset, val); + return val; } static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value, diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 46ab9323bd..a054def07c 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -18,3 +18,9 @@ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" P sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 + +# avr_gpio.c +avr_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 +avr_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 +avr_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 +avr_gpio_update_output_irq(int64_t line, int64_t value) "pin %" PRIi64 " value %" PRIi64 -- 2.17.1