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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id v13sm7794719wrt.45.2021.03.03.09.48.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 09:48:50 -0800 (PST) Date: Wed, 3 Mar 2021 17:48:49 +0000 From: Leif Lindholm To: Marcin Juszkiewicz Subject: Re: [PATCH] arm: bump amount of PMU counters to pass SBSA ACS Message-ID: <20210303174849.GF1664@vanye> References: <20210303151634.3421880-1-marcin.juszkiewicz@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210303151634.3421880-1-marcin.juszkiewicz@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=leif@nuviainc.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Mar 03, 2021 at 16:16:34 +0100, Marcin Juszkiewicz wrote: > Arm BSA (Base System Architecture) specification says: > > B_PE_09: PEs must implement the FEAT_PMUv3p1 extension, and the base > system must expose a minimum of four programmable PMU counters to the > operating system. > > B_PE_21: The base system must expose a minimum of two programmable PMU > counters to a hypervisor. > > It is then repeated in SBSA (Server Base System Architecture) > specification in level 3 requirements: > > Each PE must implement a minimum of six programmable PMU counters. > > So let make QEMU provide those 6 PMU counters. > > SBSA-ACS says now: > > 12 : Check number of PMU counters : Result: PASS > > Signed-off-by: Marcin Juszkiewicz Reviewed-by: Leif Lindholm It would be good if we could get 6.0 closer to SBSA compliance. Would it be worth the effort to make this controllable per cpu model? / Leif > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0e1a3b9421..02e25b5c22 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -38,7 +38,7 @@ > #endif > > #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ > -#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ > +#define PMCR_NUM_COUNTERS 6 /* QEMU IMPDEF choice */ > > #ifndef CONFIG_USER_ONLY > > -- > 2.29.2 >