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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id t14sm38170567wru.64.2021.03.04.05.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 05:53:06 -0800 (PST) Date: Thu, 4 Mar 2021 13:53:04 +0000 From: Leif Lindholm To: Peter Maydell Subject: Re: [PATCH] arm: bump amount of PMU counters to pass SBSA ACS Message-ID: <20210304135304.GI1664@vanye> References: <20210303151634.3421880-1-marcin.juszkiewicz@linaro.org> <20210303174849.GF1664@vanye> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=leif@nuviainc.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcin Juszkiewicz , qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Mar 03, 2021 at 18:06:46 +0000, Peter Maydell wrote: > On Wed, 3 Mar 2021 at 17:48, Leif Lindholm wrote: > > It would be good if we could get 6.0 closer to SBSA compliance. > > How far away are we at the moment ? > > > Would it be worth the effort to make this controllable per cpu model? > > I don't have a strong opinion on whether we should, but if we do then the > right way to implement that would be to have the PMCR reset value > as a reset_pmcr_el0 field in struct ARMCPU (like the existing reset_fpsid, > reset_sctlr, etc) that gets set per-CPU to whatever the CPU's value for > it is; and then instead of using a PMCR_NUM_COUNTERS value, > extract the PMCR.N field when needed. The hardest part would be > going through all the CPU TRMs to find out the correct reset value. That makes sense. I guess we could also phase the transition by using the default value if zero? Regards, Leif