From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aurelien Jarno" <aurelien@aurel32.net>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH 1/6] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize()
Date: Fri, 5 Mar 2021 17:21:02 +0100 [thread overview]
Message-ID: <20210305162107.2233203-2-f4bug@amsat.org> (raw)
In-Reply-To: <20210305162107.2233203-1-f4bug@amsat.org>
The ISD I/O region belongs to the TYPE_GT64120_PCI_HOST_BRIDGE,
so initialize it before it is realized, not after.
Rename the region as 'gt64120-isd' so it is clearer to realize
it belongs to the GT64120 in the memory tree view.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/mips/gt64xxx_pci.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 588e6f99301..6eb73e77057 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1196,6 +1196,14 @@ static void gt64120_reset(DeviceState *dev)
gt64120_pci_mapping(s);
}
+static void gt64120_realize(DeviceState *dev, Error **errp)
+{
+ GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
+
+ memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
+ "gt64120-isd", 0x1000);
+}
+
PCIBus *gt64120_register(qemu_irq *pic)
{
GT64120State *d;
@@ -1214,8 +1222,6 @@ PCIBus *gt64120_register(qemu_irq *pic)
get_system_io(),
PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d,
- "isd-mem", 0x1000);
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
return phb->bus;
@@ -1270,6 +1276,7 @@ static void gt64120_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->realize = gt64120_realize;
dc->reset = gt64120_reset;
dc->vmsd = &vmstate_gt64120;
}
--
2.26.2
next prev parent reply other threads:[~2021-03-05 16:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-05 16:21 [PATCH 0/6] hw/mips/gt64120: Minor fixes Philippe Mathieu-Daudé
2021-03-05 16:21 ` Philippe Mathieu-Daudé [this message]
2021-03-05 16:21 ` [PATCH 2/6] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers Philippe Mathieu-Daudé
2021-03-05 16:21 ` [PATCH 3/6] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats Philippe Mathieu-Daudé
2021-03-05 16:21 ` [PATCH 4/6] hw/mips/gt64xxx: Rename trace events related to interrupt registers Philippe Mathieu-Daudé
2021-03-05 16:21 ` [PATCH 5/6] hw/mips/gt64xxx: Trace accesses to ISD registers Philippe Mathieu-Daudé
2021-03-05 16:21 ` [PATCH 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole Philippe Mathieu-Daudé
2021-03-09 9:10 ` [PATCH 0/6] hw/mips/gt64120: Minor fixes Philippe Mathieu-Daudé
2021-03-09 14:04 ` BALATON Zoltan
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