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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id h62sm5259597wmf.37.2021.03.05.08.21.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Mar 2021 08:21:18 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 2/6] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers Date: Fri, 5 Mar 2021 17:21:03 +0100 Message-Id: <20210305162107.2233203-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210305162107.2233203-1-f4bug@amsat.org> References: <20210305162107.2233203-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The ISD MemoryRegion is implemented for 32-bit accesses. Simplify it by setting the MemoryRegionOps::impl min/max access size fields. Since the region is registered with a size of 0x1000 bytes, we can remove the hwaddr mask. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/gt64xxx_pci.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 6eb73e77057..99b1690af19 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -385,13 +385,12 @@ static void gt64120_writel(void *opaque, hwaddr addr, { GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); - uint32_t saddr; + uint32_t saddr = addr >> 2; if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); } - saddr = (addr & 0xfff) >> 2; switch (saddr) { /* CPU Configuration */ @@ -695,9 +694,8 @@ static uint64_t gt64120_readl(void *opaque, GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t val; - uint32_t saddr; + uint32_t saddr = addr >> 2; - saddr = (addr & 0xfff) >> 2; switch (saddr) { /* CPU Configuration */ @@ -976,6 +974,10 @@ static const MemoryRegionOps isd_mem_ops = { .read = gt64120_readl, .write = gt64120_writel, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) -- 2.26.2