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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 14/49] target/arm: Restrict v8M IDAU to TCG
Date: Fri,  5 Mar 2021 17:14:40 +0000	[thread overview]
Message-ID: <20210305171515.1038-15-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210305171515.1038-1-peter.maydell@linaro.org>

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

IDAU is specific to M-profile. KVM only supports A-profile.
Restrict this interface to TCG, as it is pointless (and
confusing) on a KVM-only build.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210221222617.2579610-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c     | 7 -------
 target/arm/cpu_tcg.c | 8 ++++++++
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 058672c9776..2666d4363d0 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2384,12 +2384,6 @@ static const TypeInfo arm_cpu_type_info = {
     .class_init = arm_cpu_class_init,
 };
 
-static const TypeInfo idau_interface_type_info = {
-    .name = TYPE_IDAU_INTERFACE,
-    .parent = TYPE_INTERFACE,
-    .class_size = sizeof(IDAUInterfaceClass),
-};
-
 static void arm_cpu_register_types(void)
 {
     const size_t cpu_count = ARRAY_SIZE(arm_cpus);
@@ -2403,7 +2397,6 @@ static void arm_cpu_register_types(void)
     if (cpu_count) {
         size_t i;
 
-        type_register_static(&idau_interface_type_info);
         for (i = 0; i < cpu_count; ++i) {
             arm_cpu_register(&arm_cpus[i]);
         }
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index c29b434c60d..fb07a336939 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -14,6 +14,7 @@
 #include "hw/core/tcg-cpu-ops.h"
 #endif /* CONFIG_TCG */
 #include "internals.h"
+#include "target/arm/idau.h"
 
 /* CPU models. These are not needed for the AArch64 linux-user build. */
 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
@@ -739,10 +740,17 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 };
 
+static const TypeInfo idau_interface_type_info = {
+    .name = TYPE_IDAU_INTERFACE,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(IDAUInterfaceClass),
+};
+
 static void arm_tcg_cpu_register_types(void)
 {
     size_t i;
 
+    type_register_static(&idau_interface_type_info);
     for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
         arm_cpu_register(&arm_tcg_cpus[i]);
     }
-- 
2.20.1



  parent reply	other threads:[~2021-03-05 17:42 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-05 17:14 [PULL 00/49] target-arm queue Peter Maydell
2021-03-05 17:14 ` [PULL 01/49] sbsa-ref: remove cortex-a53 from list of supported cpus Peter Maydell
2021-03-05 17:14 ` [PULL 02/49] sbsa-ref: add 'max' to list of allowed cpus Peter Maydell
2021-03-05 17:14 ` [PULL 03/49] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe Peter Maydell
2021-03-05 17:14 ` [PULL 04/49] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU Peter Maydell
2021-03-05 17:14 ` [PULL 05/49] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU Peter Maydell
2021-03-05 17:14 ` [PULL 06/49] hw/net: Add npcm7xx emc model Peter Maydell
2021-03-05 17:14 ` [PULL 07/49] hw/arm: " Peter Maydell
2021-03-05 17:14 ` [PULL 08/49] tests/qtests: Add npcm7xx emc model test Peter Maydell
2021-03-05 17:14 ` [PULL 09/49] hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property Peter Maydell
2021-03-05 17:14 ` [PULL 10/49] target/arm: Speed up aarch64 TBL/TBX Peter Maydell
2021-03-05 17:14 ` [PULL 11/49] hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init() Peter Maydell
2021-03-05 17:14 ` [PULL 12/49] virtio-mmio: improve virtio-mmio get_dev_path alog Peter Maydell
2021-03-05 17:14 ` [PULL 13/49] target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks Peter Maydell
2021-03-05 17:14 ` Peter Maydell [this message]
2021-03-05 17:14 ` [PULL 15/49] target/arm/cpu: Update coding style to make checkpatch.pl happy Peter Maydell
2021-03-05 17:14 ` [PULL 16/49] hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces Peter Maydell
2021-03-05 17:14 ` [PULL 17/49] hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces Peter Maydell
2021-03-05 17:14 ` [PULL 18/49] hw/display/tc6393xb: Expand out macros in template header Peter Maydell
2021-03-05 17:14 ` [PULL 19/49] hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite Peter Maydell
2021-03-05 17:14 ` [PULL 20/49] hw/display/omap_lcdc: Expand out macros in template header Peter Maydell
2021-03-05 17:14 ` [PULL 21/49] hw/display/omap_lcdc: Drop broken bigendian ifdef Peter Maydell
2021-03-05 17:14 ` [PULL 22/49] hw/display/omap_lcdc: Fix coding style issues in template header Peter Maydell
2021-03-05 17:14 ` [PULL 23/49] hw/display/omap_lcdc: Inline template header into C file Peter Maydell
2021-03-05 17:14 ` [PULL 24/49] hw/display/omap_lcdc: Delete unnecessary macro Peter Maydell
2021-03-05 17:14 ` [PULL 25/49] hw/display/tcx: Drop unnecessary code for handling BGR format outputs Peter Maydell
2021-03-05 17:14 ` [PULL 26/49] hw/arm/mps2-tz: Make SYSCLK frequency board-specific Peter Maydell
2021-03-05 17:14 ` [PULL 27/49] hw/misc/mps2-scc: Support configurable number of OSCCLK values Peter Maydell
2021-03-05 17:14 ` [PULL 28/49] hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511 Peter Maydell
2021-03-05 17:14 ` [PULL 29/49] hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board Peter Maydell
2021-03-05 17:14 ` [PULL 30/49] hw/misc/mps2-fpgaio: Make number of LEDs configurable by board Peter Maydell
2021-03-05 17:14 ` [PULL 31/49] hw/misc/mps2-fpgaio: Support SWITCH register Peter Maydell
2021-03-05 17:14 ` [PULL 32/49] hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board Peter Maydell
2021-03-05 17:14 ` [PULL 33/49] hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type Peter Maydell
2021-03-05 17:15 ` [PULL 34/49] hw/arm/mps2-tz: Make number of IRQs board-specific Peter Maydell
2021-03-05 17:15 ` [PULL 35/49] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 Peter Maydell
2021-03-05 17:15 ` [PULL 36/49] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI Peter Maydell
2021-03-05 17:15 ` [PULL 37/49] hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts Peter Maydell
2021-03-05 17:15 ` [PULL 38/49] hw/arm/mps2-tz: Move device IRQ info to data structures Peter Maydell
2021-03-05 17:15 ` [PULL 39/49] hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs Peter Maydell
2021-03-05 17:15 ` [PULL 40/49] hw/arm/mps2-tz: Allow boards to have different PPCInfo data Peter Maydell
2021-03-05 17:15 ` [PULL 41/49] hw/arm/mps2-tz: Make RAM arrangement board-specific Peter Maydell
2021-03-05 17:15 ` [PULL 42/49] hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data Peter Maydell
2021-03-05 17:15 ` [PULL 43/49] hw/arm/mps2-tz: Support ROMs as well as RAMs Peter Maydell
2021-03-05 17:15 ` [PULL 44/49] hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo Peter Maydell
2021-03-05 17:15 ` [PULL 45/49] hw/arm/mps2-tz: Add new mps3-an524 board Peter Maydell
2021-03-05 17:15 ` [PULL 46/49] hw/arm/mps2-tz: Stub out USB controller for mps3-an524 Peter Maydell
2021-03-05 17:15 ` [PULL 47/49] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 Peter Maydell
2021-03-05 17:15 ` [PULL 48/49] docs/system/arm/mps2.rst: Document the new mps3-an524 board Peter Maydell
2021-03-05 17:15 ` [PULL 49/49] hw/arm/mps2: Update old infocenter.arm.com URLs Peter Maydell
2021-03-05 18:36 ` [PULL 00/49] target-arm queue no-reply

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