From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 39/49] hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs
Date: Fri, 5 Mar 2021 17:15:05 +0000 [thread overview]
Message-ID: <20210305171515.1038-40-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210305171515.1038-1-peter.maydell@linaro.org>
We create an OR gate to wire together the overflow IRQs for all the
UARTs on the board; this has to have twice the number of inputs as
there are UARTs, since each UART feeds it a TX overflow and an RX
overflow interrupt line. Replace the hardcoded '10' with a
calculation based on the size of the uart[] array in the
MPS2TZMachineState. (We rely on OR gate inputs that are never wired
up or asserted being treated as always-zero.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-15-peter.maydell@linaro.org
---
hw/arm/mps2-tz.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 53886d66b61..1c1fc34dd53 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -516,13 +516,18 @@ static void mps2tz_common_init(MachineState *machine)
*/
memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
- /* The overflow IRQs for all UARTs are ORed together.
+ /*
+ * The overflow IRQs for all UARTs are ORed together.
* Tx, Rx and "combined" IRQs are sent to the NVIC separately.
- * Create the OR gate for this.
+ * Create the OR gate for this: it has one input for the TX overflow
+ * and one for the RX overflow for each UART we might have.
+ * (If the board has fewer than the maximum possible number of UARTs
+ * those inputs are never wired up and are treated as always-zero.)
*/
object_initialize_child(OBJECT(mms), "uart-irq-orgate",
&mms->uart_irq_orgate, TYPE_OR_IRQ);
- object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10,
+ object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines",
+ 2 * ARRAY_SIZE(mms->uart),
&error_fatal);
qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
--
2.20.1
next prev parent reply other threads:[~2021-03-05 18:25 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-05 17:14 [PULL 00/49] target-arm queue Peter Maydell
2021-03-05 17:14 ` [PULL 01/49] sbsa-ref: remove cortex-a53 from list of supported cpus Peter Maydell
2021-03-05 17:14 ` [PULL 02/49] sbsa-ref: add 'max' to list of allowed cpus Peter Maydell
2021-03-05 17:14 ` [PULL 03/49] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe Peter Maydell
2021-03-05 17:14 ` [PULL 04/49] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU Peter Maydell
2021-03-05 17:14 ` [PULL 05/49] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU Peter Maydell
2021-03-05 17:14 ` [PULL 06/49] hw/net: Add npcm7xx emc model Peter Maydell
2021-03-05 17:14 ` [PULL 07/49] hw/arm: " Peter Maydell
2021-03-05 17:14 ` [PULL 08/49] tests/qtests: Add npcm7xx emc model test Peter Maydell
2021-03-05 17:14 ` [PULL 09/49] hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property Peter Maydell
2021-03-05 17:14 ` [PULL 10/49] target/arm: Speed up aarch64 TBL/TBX Peter Maydell
2021-03-05 17:14 ` [PULL 11/49] hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init() Peter Maydell
2021-03-05 17:14 ` [PULL 12/49] virtio-mmio: improve virtio-mmio get_dev_path alog Peter Maydell
2021-03-05 17:14 ` [PULL 13/49] target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks Peter Maydell
2021-03-05 17:14 ` [PULL 14/49] target/arm: Restrict v8M IDAU to TCG Peter Maydell
2021-03-05 17:14 ` [PULL 15/49] target/arm/cpu: Update coding style to make checkpatch.pl happy Peter Maydell
2021-03-05 17:14 ` [PULL 16/49] hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces Peter Maydell
2021-03-05 17:14 ` [PULL 17/49] hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces Peter Maydell
2021-03-05 17:14 ` [PULL 18/49] hw/display/tc6393xb: Expand out macros in template header Peter Maydell
2021-03-05 17:14 ` [PULL 19/49] hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite Peter Maydell
2021-03-05 17:14 ` [PULL 20/49] hw/display/omap_lcdc: Expand out macros in template header Peter Maydell
2021-03-05 17:14 ` [PULL 21/49] hw/display/omap_lcdc: Drop broken bigendian ifdef Peter Maydell
2021-03-05 17:14 ` [PULL 22/49] hw/display/omap_lcdc: Fix coding style issues in template header Peter Maydell
2021-03-05 17:14 ` [PULL 23/49] hw/display/omap_lcdc: Inline template header into C file Peter Maydell
2021-03-05 17:14 ` [PULL 24/49] hw/display/omap_lcdc: Delete unnecessary macro Peter Maydell
2021-03-05 17:14 ` [PULL 25/49] hw/display/tcx: Drop unnecessary code for handling BGR format outputs Peter Maydell
2021-03-05 17:14 ` [PULL 26/49] hw/arm/mps2-tz: Make SYSCLK frequency board-specific Peter Maydell
2021-03-05 17:14 ` [PULL 27/49] hw/misc/mps2-scc: Support configurable number of OSCCLK values Peter Maydell
2021-03-05 17:14 ` [PULL 28/49] hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511 Peter Maydell
2021-03-05 17:14 ` [PULL 29/49] hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board Peter Maydell
2021-03-05 17:14 ` [PULL 30/49] hw/misc/mps2-fpgaio: Make number of LEDs configurable by board Peter Maydell
2021-03-05 17:14 ` [PULL 31/49] hw/misc/mps2-fpgaio: Support SWITCH register Peter Maydell
2021-03-05 17:14 ` [PULL 32/49] hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board Peter Maydell
2021-03-05 17:14 ` [PULL 33/49] hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type Peter Maydell
2021-03-05 17:15 ` [PULL 34/49] hw/arm/mps2-tz: Make number of IRQs board-specific Peter Maydell
2021-03-05 17:15 ` [PULL 35/49] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 Peter Maydell
2021-03-05 17:15 ` [PULL 36/49] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI Peter Maydell
2021-03-05 17:15 ` [PULL 37/49] hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts Peter Maydell
2021-03-05 17:15 ` [PULL 38/49] hw/arm/mps2-tz: Move device IRQ info to data structures Peter Maydell
2021-03-05 17:15 ` Peter Maydell [this message]
2021-03-05 17:15 ` [PULL 40/49] hw/arm/mps2-tz: Allow boards to have different PPCInfo data Peter Maydell
2021-03-05 17:15 ` [PULL 41/49] hw/arm/mps2-tz: Make RAM arrangement board-specific Peter Maydell
2021-03-05 17:15 ` [PULL 42/49] hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data Peter Maydell
2021-03-05 17:15 ` [PULL 43/49] hw/arm/mps2-tz: Support ROMs as well as RAMs Peter Maydell
2021-03-05 17:15 ` [PULL 44/49] hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo Peter Maydell
2021-03-05 17:15 ` [PULL 45/49] hw/arm/mps2-tz: Add new mps3-an524 board Peter Maydell
2021-03-05 17:15 ` [PULL 46/49] hw/arm/mps2-tz: Stub out USB controller for mps3-an524 Peter Maydell
2021-03-05 17:15 ` [PULL 47/49] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 Peter Maydell
2021-03-05 17:15 ` [PULL 48/49] docs/system/arm/mps2.rst: Document the new mps3-an524 board Peter Maydell
2021-03-05 17:15 ` [PULL 49/49] hw/arm/mps2: Update old infocenter.arm.com URLs Peter Maydell
2021-03-05 18:36 ` [PULL 00/49] target-arm queue no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210305171515.1038-40-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).