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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 20/27] tcg/tci: Merge extension operations
Date: Sat,  6 Mar 2021 13:36:06 -0800	[thread overview]
Message-ID: <20210306213613.85168-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org>

This includes ext8s, ext8u, ext16s, ext16u.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tci.c | 44 ++++++++------------------------------------
 1 file changed, 8 insertions(+), 36 deletions(-)

diff --git a/tcg/tci.c b/tcg/tci.c
index d0bf810781..73f639d23a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -607,29 +607,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
             break;
 #endif /* TCG_TARGET_REG_BITS == 32 */
-#if TCG_TARGET_HAS_ext8s_i32
-        case INDEX_op_ext8s_i32:
+#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
+        CASE_32_64(ext8s)
             t0 = *tb_ptr++;
             t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, (int8_t)t1);
             break;
 #endif
-#if TCG_TARGET_HAS_ext16s_i32
-        case INDEX_op_ext16s_i32:
+#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
+        CASE_32_64(ext16s)
             t0 = *tb_ptr++;
             t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, (int16_t)t1);
             break;
 #endif
-#if TCG_TARGET_HAS_ext8u_i32
-        case INDEX_op_ext8u_i32:
+#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
+        CASE_32_64(ext8u)
             t0 = *tb_ptr++;
             t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, (uint8_t)t1);
             break;
 #endif
-#if TCG_TARGET_HAS_ext16u_i32
-        case INDEX_op_ext16u_i32:
+#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
+        CASE_32_64(ext16u)
             t0 = *tb_ptr++;
             t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, (uint16_t)t1);
@@ -779,34 +779,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
                 continue;
             }
             break;
-#if TCG_TARGET_HAS_ext8u_i64
-        case INDEX_op_ext8u_i64:
-            t0 = *tb_ptr++;
-            t1 = tci_read_r(regs, &tb_ptr);
-            tci_write_reg(regs, t0, (uint8_t)t1);
-            break;
-#endif
-#if TCG_TARGET_HAS_ext8s_i64
-        case INDEX_op_ext8s_i64:
-            t0 = *tb_ptr++;
-            t1 = tci_read_r(regs, &tb_ptr);
-            tci_write_reg(regs, t0, (int8_t)t1);
-            break;
-#endif
-#if TCG_TARGET_HAS_ext16s_i64
-        case INDEX_op_ext16s_i64:
-            t0 = *tb_ptr++;
-            t1 = tci_read_r(regs, &tb_ptr);
-            tci_write_reg(regs, t0, (int16_t)t1);
-            break;
-#endif
-#if TCG_TARGET_HAS_ext16u_i64
-        case INDEX_op_ext16u_i64:
-            t0 = *tb_ptr++;
-            t1 = tci_read_r(regs, &tb_ptr);
-            tci_write_reg(regs, t0, (uint16_t)t1);
-            break;
-#endif
 #if TCG_TARGET_HAS_ext32s_i64
         case INDEX_op_ext32s_i64:
 #endif
-- 
2.25.1



  parent reply	other threads:[~2021-03-06 21:45 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-06 21:35 [PULL 00/27] tcg patch queue Richard Henderson
2021-03-06 21:35 ` [PULL 01/27] tcg/aarch64: Fix constant subtraction in tcg_out_addsub2 Richard Henderson
2021-03-06 21:35 ` [PULL 02/27] tcg/aarch64: Fix I3617_CMLE0 Richard Henderson
2021-03-06 21:35 ` [PULL 03/27] tcg/aarch64: Fix generation of "scalar" vector operations Richard Henderson
2021-03-06 21:35 ` [PULL 04/27] tcg/tci: Use exec/cpu_ldst.h interfaces Richard Henderson
2021-03-06 21:35 ` [PULL 05/27] tcg: Split out tcg_raise_tb_overflow Richard Henderson
2021-03-06 21:35 ` [PULL 06/27] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Richard Henderson
2021-03-06 21:35 ` [PULL 07/27] tcg/tci: Merge identical cases in generation (arithmetic opcodes) Richard Henderson
2021-03-06 21:35 ` [PULL 08/27] tcg/tci: Merge identical cases in generation (exchange opcodes) Richard Henderson
2021-03-06 21:35 ` [PULL 09/27] tcg/tci: Merge identical cases in generation (deposit opcode) Richard Henderson
2021-03-06 21:35 ` [PULL 10/27] tcg/tci: Merge identical cases in generation (conditional opcodes) Richard Henderson
2021-03-06 21:35 ` [PULL 11/27] tcg/tci: Merge identical cases in generation (load/store opcodes) Richard Henderson
2021-03-06 21:35 ` [PULL 12/27] tcg/tci: Remove tci_read_r8 Richard Henderson
2021-03-06 21:35 ` [PULL 13/27] tcg/tci: Remove tci_read_r8s Richard Henderson
2021-03-06 21:36 ` [PULL 14/27] tcg/tci: Remove tci_read_r16 Richard Henderson
2021-03-06 21:36 ` [PULL 15/27] tcg/tci: Remove tci_read_r16s Richard Henderson
2021-03-06 21:36 ` [PULL 16/27] tcg/tci: Remove tci_read_r32 Richard Henderson
2021-03-06 21:36 ` [PULL 17/27] tcg/tci: Remove tci_read_r32s Richard Henderson
2021-03-06 21:36 ` [PULL 18/27] tcg/tci: Reduce use of tci_read_r64 Richard Henderson
2021-03-06 21:36 ` [PULL 19/27] tcg/tci: Merge basic arithmetic operations Richard Henderson
2021-03-06 21:36 ` Richard Henderson [this message]
2021-03-06 21:36 ` [PULL 21/27] tcg/tci: Merge bswap operations Richard Henderson
2021-03-06 21:36 ` [PULL 22/27] tcg/tci: Merge mov, not and neg operations Richard Henderson
2021-03-06 21:36 ` [PULL 23/27] accel/tcg: rename tb_lookup__cpu_state and hoist state extraction Richard Henderson
2021-03-06 21:36 ` [PULL 24/27] accel/tcg: move CF_CLUSTER calculation to curr_cflags Richard Henderson
2021-03-06 21:36 ` [PULL 25/27] accel/tcg: drop the use of CF_HASH_MASK and rename params Richard Henderson
2021-03-06 21:36 ` [PULL 26/27] include/exec: lightly re-arrange TranslationBlock Richard Henderson
2021-03-06 21:36 ` [PULL 27/27] accel/tcg: Precompute curr_cflags into cpu->tcg_cflags Richard Henderson
2021-03-09 11:21 ` [PULL 00/27] tcg patch queue Peter Maydell

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