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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/54] hw/arm/mps2-tz: Make UART overflow IRQ board-specific Date: Mon, 8 Mar 2021 17:32:26 +0000 Message-Id: <20210308173244.20710-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The AN547 puts the combined UART overflow IRQ at 48, not 47 like the other images. Make this setting board-specific. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-37-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 72da8cb1a16..85e80c4d726 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -111,6 +111,7 @@ struct MPS2TZMachineClass { uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */ int numirq; /* Number of external interrupts */ + int uart_overflow_irq; /* number of the combined UART overflow IRQ */ const RAMInfo *raminfo; const char *armsse_type; }; @@ -770,7 +771,7 @@ static void mps2tz_common_init(MachineState *machine) &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, - get_sse_irq_in(mms, 47)); + get_sse_irq_in(mms, mmc->uart_overflow_irq)); /* Most of the devices in the FPGA are behind Peripheral Protection * Controllers. The required order for initializing things is: @@ -1046,6 +1047,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->fpgaio_num_leds = 2; mmc->fpgaio_has_switches = false; mmc->numirq = 92; + mmc->uart_overflow_irq = 47; mmc->raminfo = an505_raminfo; mmc->armsse_type = TYPE_IOTKIT; mps2tz_set_default_ram_info(mmc); @@ -1069,6 +1071,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->fpgaio_num_leds = 2; mmc->fpgaio_has_switches = false; mmc->numirq = 92; + mmc->uart_overflow_irq = 47; mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type = TYPE_SSE200; mps2tz_set_default_ram_info(mmc); @@ -1092,6 +1095,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) mmc->fpgaio_num_leds = 10; mmc->fpgaio_has_switches = true; mmc->numirq = 95; + mmc->uart_overflow_irq = 47; mmc->raminfo = an524_raminfo; mmc->armsse_type = TYPE_SSE200; mps2tz_set_default_ram_info(mmc); -- 2.20.1