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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id s11sm3065335edt.27.2021.03.09.06.26.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Mar 2021 06:26:57 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH RESEND 5/6] hw/mips/gt64xxx: Trace accesses to ISD registers Date: Tue, 9 Mar 2021 15:26:29 +0100 Message-Id: <20210309142630.728014-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210309142630.728014-1-f4bug@amsat.org> References: <20210309142630.728014-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Trace all accesses to Internal Space Decode (ISD) registers. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/gt64xxx_pci.c | 2 ++ hw/mips/trace-events | 2 ++ 2 files changed, 4 insertions(+) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 9a12d00d1e1..43349d6837d 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -387,6 +387,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t saddr = addr >> 2; + trace_gt64120_write(addr, val); if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); } @@ -966,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque, if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); } + trace_gt64120_read(addr, val); return val; } diff --git a/hw/mips/trace-events b/hw/mips/trace-events index b7e934c3933..13ee731a488 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,6 @@ # gt64xxx_pci.c +gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 +gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 -- 2.26.2