From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Laurent Desnogues <laurent.desnogues@gmail.com>,
peter.maydell@linaro.org, qemu-arm@nongnu.org,
alex.bennee@linaro.org
Subject: [PATCH v4 1/8] target/arm: Fix sve_uzp_p vs odd vector lengths
Date: Tue, 9 Mar 2021 07:52:58 -0800 [thread overview]
Message-ID: <20210309155305.11301-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210309155305.11301-1-richard.henderson@linaro.org>
Missed out on compressing the second half of a predicate
with length vl % 512 > 256.
Adjust all of the x + (y << s) to x | (y << s) as a
general style fix. Drop the extract64 because the input
uint64_t are known to be already zero-extended from the
current size of the predicate.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve_helper.c | 30 +++++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 844db08bd5..11c9397dbb 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -1939,7 +1939,7 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
if (oprsz <= 8) {
l = compress_bits(n[0] >> odd, esz);
h = compress_bits(m[0] >> odd, esz);
- d[0] = extract64(l + (h << (4 * oprsz)), 0, 8 * oprsz);
+ d[0] = l | (h << (4 * oprsz));
} else {
ARMPredicateReg tmp_m;
intptr_t oprsz_16 = oprsz / 16;
@@ -1953,23 +1953,35 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
h = n[2 * i + 1];
l = compress_bits(l >> odd, esz);
h = compress_bits(h >> odd, esz);
- d[i] = l + (h << 32);
+ d[i] = l | (h << 32);
}
- /* For VL which is not a power of 2, the results from M do not
- align nicely with the uint64_t for D. Put the aligned results
- from M into TMP_M and then copy it into place afterward. */
+ /*
+ * For VL which is not a multiple of 512, the results from M do not
+ * align nicely with the uint64_t for D. Put the aligned results
+ * from M into TMP_M and then copy it into place afterward.
+ */
if (oprsz & 15) {
- d[i] = compress_bits(n[2 * i] >> odd, esz);
+ int final_shift = (oprsz & 15) * 2;
+
+ l = n[2 * i + 0];
+ h = n[2 * i + 1];
+ l = compress_bits(l >> odd, esz);
+ h = compress_bits(h >> odd, esz);
+ d[i] = l | (h << final_shift);
for (i = 0; i < oprsz_16; i++) {
l = m[2 * i + 0];
h = m[2 * i + 1];
l = compress_bits(l >> odd, esz);
h = compress_bits(h >> odd, esz);
- tmp_m.p[i] = l + (h << 32);
+ tmp_m.p[i] = l | (h << 32);
}
- tmp_m.p[i] = compress_bits(m[2 * i] >> odd, esz);
+ l = m[2 * i + 0];
+ h = m[2 * i + 1];
+ l = compress_bits(l >> odd, esz);
+ h = compress_bits(h >> odd, esz);
+ tmp_m.p[i] = l | (h << final_shift);
swap_memmove(vd + oprsz / 2, &tmp_m, oprsz / 2);
} else {
@@ -1978,7 +1990,7 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
h = m[2 * i + 1];
l = compress_bits(l >> odd, esz);
h = compress_bits(h >> odd, esz);
- d[oprsz_16 + i] = l + (h << 32);
+ d[oprsz_16 + i] = l | (h << 32);
}
}
}
--
2.25.1
next prev parent reply other threads:[~2021-03-09 16:37 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-09 15:52 [PATCH v4 0/8] target/arm: sve1 fixes Richard Henderson
2021-03-09 15:52 ` Richard Henderson [this message]
2021-03-09 15:52 ` [PATCH v4 2/8] target/arm: Fix sve_zip_p vs odd vector lengths Richard Henderson
2021-03-09 15:53 ` [PATCH v4 3/8] target/arm: Fix sve_punpk_p " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 4/8] target/arm: Update find_last_active for PREDDESC Richard Henderson
2021-03-09 15:53 ` [PATCH v4 5/8] target/arm: Update BRKA, BRKB, BRKN " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 6/8] target/arm: Update CNTP " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 7/8] target/arm: Update WHILE " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 8/8] target/arm: Update sve reduction vs simd_desc Richard Henderson
2021-03-11 13:28 ` [PATCH v4 0/8] target/arm: sve1 fixes Peter Maydell
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