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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [PATCH v4 4/8] target/arm: Update find_last_active for PREDDESC
Date: Tue,  9 Mar 2021 07:53:01 -0800	[thread overview]
Message-ID: <20210309155305.11301-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210309155305.11301-1-richard.henderson@linaro.org>

Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/sve_helper.c    | 6 +++---
 target/arm/translate-sve.c | 7 +++----
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 981895a17c..224c767944 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2237,10 +2237,10 @@ void HELPER(sve_compact_d)(void *vd, void *vn, void *vg, uint32_t desc)
  */
 int32_t HELPER(sve_last_active_element)(void *vg, uint32_t pred_desc)
 {
-    intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
-    intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
+    intptr_t words = DIV_ROUND_UP(FIELD_EX32(pred_desc, PREDDESC, OPRSZ), 8);
+    intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
 
-    return last_active_element(vg, DIV_ROUND_UP(oprsz, 8), esz);
+    return last_active_element(vg, words, esz);
 }
 
 void HELPER(sve_splice)(void *vd, void *vn, void *vm, void *vg, uint32_t desc)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 27402af23c..cac8082156 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -2302,11 +2302,10 @@ static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg)
      */
     TCGv_ptr t_p = tcg_temp_new_ptr();
     TCGv_i32 t_desc;
-    unsigned vsz = pred_full_reg_size(s);
-    unsigned desc;
+    unsigned desc = 0;
 
-    desc = vsz - 2;
-    desc = deposit32(desc, SIMD_DATA_SHIFT, 2, esz);
+    desc = FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s));
+    desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
 
     tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg));
     t_desc = tcg_const_i32(desc);
-- 
2.25.1



  parent reply	other threads:[~2021-03-09 16:34 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-09 15:52 [PATCH v4 0/8] target/arm: sve1 fixes Richard Henderson
2021-03-09 15:52 ` [PATCH v4 1/8] target/arm: Fix sve_uzp_p vs odd vector lengths Richard Henderson
2021-03-09 15:52 ` [PATCH v4 2/8] target/arm: Fix sve_zip_p " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 3/8] target/arm: Fix sve_punpk_p " Richard Henderson
2021-03-09 15:53 ` Richard Henderson [this message]
2021-03-09 15:53 ` [PATCH v4 5/8] target/arm: Update BRKA, BRKB, BRKN for PREDDESC Richard Henderson
2021-03-09 15:53 ` [PATCH v4 6/8] target/arm: Update CNTP " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 7/8] target/arm: Update WHILE " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 8/8] target/arm: Update sve reduction vs simd_desc Richard Henderson
2021-03-11 13:28 ` [PATCH v4 0/8] target/arm: sve1 fixes Peter Maydell

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