From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [PATCH v4 6/8] target/arm: Update CNTP for PREDDESC
Date: Tue, 9 Mar 2021 07:53:03 -0800 [thread overview]
Message-ID: <20210309155305.11301-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210309155305.11301-1-richard.henderson@linaro.org>
Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve_helper.c | 6 +++---
target/arm/translate-sve.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 8e0a5d30a5..a95bbece4f 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2836,12 +2836,12 @@ uint32_t HELPER(sve_brkns)(void *vd, void *vn, void *vg, uint32_t pred_desc)
uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc)
{
- intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
- intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
+ intptr_t words = DIV_ROUND_UP(FIELD_EX32(pred_desc, PREDDESC, OPRSZ), 8);
+ intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
uint64_t *n = vn, *g = vg, sum = 0, mask = pred_esz_masks[esz];
intptr_t i;
- for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) {
+ for (i = 0; i < words; ++i) {
uint64_t t = n[i] & g[i] & mask;
sum += ctpop64(t);
}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index c0212e6b08..722805cf99 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -2967,11 +2967,11 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
} else {
TCGv_ptr t_pn = tcg_temp_new_ptr();
TCGv_ptr t_pg = tcg_temp_new_ptr();
- unsigned desc;
+ unsigned desc = 0;
TCGv_i32 t_desc;
- desc = psz - 2;
- desc = deposit32(desc, SIMD_DATA_SHIFT, 2, esz);
+ desc = FIELD_DP32(desc, PREDDESC, OPRSZ, psz);
+ desc = FIELD_DP32(desc, PREDDESC, ESZ, esz);
tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn));
tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
--
2.25.1
next prev parent reply other threads:[~2021-03-09 16:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-09 15:52 [PATCH v4 0/8] target/arm: sve1 fixes Richard Henderson
2021-03-09 15:52 ` [PATCH v4 1/8] target/arm: Fix sve_uzp_p vs odd vector lengths Richard Henderson
2021-03-09 15:52 ` [PATCH v4 2/8] target/arm: Fix sve_zip_p " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 3/8] target/arm: Fix sve_punpk_p " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 4/8] target/arm: Update find_last_active for PREDDESC Richard Henderson
2021-03-09 15:53 ` [PATCH v4 5/8] target/arm: Update BRKA, BRKB, BRKN " Richard Henderson
2021-03-09 15:53 ` Richard Henderson [this message]
2021-03-09 15:53 ` [PATCH v4 7/8] target/arm: Update WHILE " Richard Henderson
2021-03-09 15:53 ` [PATCH v4 8/8] target/arm: Update sve reduction vs simd_desc Richard Henderson
2021-03-11 13:28 ` [PATCH v4 0/8] target/arm: sve1 fixes Peter Maydell
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